Semiconductor package with integrated die paddles for power stage

Patent metadata

Field	Value
Publication number	US-9564389-B2
Application number	US-201514631745-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Mar 18, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

In one implementation, a semiconductor package includes a first conductive carrier including a first die paddle of the semiconductor package, and a control transistor having a drain attached to the first die paddle. The semiconductor package also includes a second conductive carrier attached to the first conductive carrier and including a second die paddle of the semiconductor package, and a sync transistor having a drain attached to the second die paddle. The second die paddle couples a source of the control transistor to the drain of the sync transistor.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a first conductive carrier including a first die paddle of said semiconductor package;
a control transistor having a drain attached to said first die paddle;
a second conductive carrier attached to said first conductive carrier and including a second die paddle of said semiconductor package;
a sync transistor having a drain attached to said second die paddle;
said second die paddle being further attached to a source of said control transistor so as to couple said source of said control transistor to said drain of said sync transistor.

2. The semiconductor package of claim 1 , wherein said second die paddle is configured as an integrated head spreader for said semiconductor package.

3. The semiconductor package of claim 1 , wherein said control transistor and said sync transistor form a power switching stage of a voltage converter.

4. The semiconductor package of claim 1 , wherein said first conductive carrier has a reduced thickness.

5. The semiconductor package of claim 1 , wherein said first conductive carrier comprises at least a portion of a partially etched lead frame.

6. The semiconductor package of claim 1 , wherein said control transistor and said sync transistor comprise silicon field-effect transistors (FETs).

7. The semiconductor package of claim 1 , wherein said control transistor and said sync transistor comprise III-Nitride high electron mobility transistors (HEMTs).

8. The semiconductor package of claim 1 , wherein said second conductive carrier is configured to connect said first conductive carrier, said control transistor, and said sync transistor to a mounting surface for said semiconductor package.

9. The semiconductor package of claim 3 , wherein said second die paddle provides a switch node of said power switching stage.

10. The semiconductor package of claim 5 , wherein said partially etched lead frame is substantially half-etched.

11. A semiconductor package comprising:
a first conductive carrier including a first die paddle;
a control transistor having a drain attached to said first die paddle;
a second conductive carrier including a second die paddle attached to a source of said control transistor;
a sync transistor having a drain attached to said second die paddle.

12. The semiconductor package of claim 11 , wherein said second die paddle is configured as an integrated heat spreader for said semiconductor package.

13. The semiconductor package of claim 11 , wherein said control transistor and said sync transistor form a power switching stage of a voltage converter.

14. The semiconductor package of claim 11 , wherein said first conductive carrier comprises at least a portion of a partially etched lead frame.

15. The semiconductor package of claim 11 , wherein said control transistor and said sync transistor comprise silicon field-effect transistors (FETs).

16. The semiconductor package of claim 11 , wherein said control transistor and said sync transistor comprise III-Nitride high electron mobility transistors (HEMTs).

17. The semiconductor package of claim 11 , wherein said second conductive carrier is configured to connect said first conductive carrier, said control transistor, and said sync transistor to a mounting surface for said semiconductor package.

18. The semiconductor package of claim 14 , wherein said partially etched lead frame is substantially half-etched.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Abaca Aida
• Guanzon Jobel A

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/427

  Bent parts · CPC title

• H10W70/442

  of multiple leadframes in a single chip · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title