Technique for determining performance characteristics of electronic devices and systems

Patent metadata

Field	Value
Publication number	US-9562934-B2
Application number	US-201313920368-A
Country	US
Kind code	B2
Filing date	Jun 18, 2013
Priority date	Mar 7, 2001
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

First claim

The invention claimed is:

1. A transmitter integrated circuit for use in a signaling system in which the transmitter integrated circuit is to be coupled to a receiver integrated circuit via transmission lines that form a digital bus, the transmitter integrated circuit comprising:
data transmitters to each transmit data over respective ones of the transmission lines to the receiver integrated circuit;
each of the data transmitters to transmit in parallel a test data signal to the receiver integrated circuit to determine a performance characteristic of the signaling system.

2. The transmitter integrated circuit of claim 1 , where each data transmitter comprises a pulse generator to generate a single bit pulse as the test data signal transmitted by the respective data transmitter.

3. The transmitter integrated circuit of claim 1 , where:
the transmission lines are aggressor transmission lines;
the signaling system is such that the transmitter integrated circuit is to be coupled to the receiver integrated circuit also via a victim transmission line of the digital bus;
the data transmitters are aggressor-line data transmitters;
the transmitter integrated circuit further comprises a victim-line data transmitter to transmit data over the victim transmission line to the receiver integrated circuit; and
the victim-line data transmitter is to remain inactive when each of the aggressor-line data transmitters are to transmit in parallel a test data signals to the receiver integrated circuit.

4. The transmitter integrated circuit of claim 3 , where the transmitter integrated circuit is to cause the aggressor-line data transmitters to transmit the test data signals to the receiver integrated circuit in association with a signaling system operation in which the receiver integrated circuit is to measure, on a receiver coupled to the victim transmission line, a response to the transmitting of the test data signal by the aggressor-line data transmitters.

5. The transmitter integrated circuit of claim 1 , where the data transmitters are to transmit the test data signals in a manner that is synchronized across the data transmitters, and where the performance characteristic is a characteristic that affects relative transmission of data over respective ones of the transmission lines.

6. The transmitter integrated circuit of claim 1 , where the transmitter integrated circuit further comprises a processor in the signaling system and where the transmitter integrated circuit is to cause the test data signal to be transmitted by each data transmitter to determine the performance characteristic of the signaling system.

7. The transmitter integrated circuit of claim 1 , where the test data signal is common to each of the data transmitters.

8. A transmitter integrated circuit for use in a signaling system in which the transmitter integrated circuit is to be coupled to a receiver integrated circuit via transmission lines that form a digital bus, the transmission lines including both aggressor transmission lines and a victim transmission line, the transmitter integrated circuit comprising:
aggressor-line data transmitters to each transmit data over respective ones of the aggressor transmission lines to the receiver integrated circuit, and a victim-line data transmitter to transmit data over the victim transmission line to the receiver integrated circuit;
each of the aggressor-line data transmitters to transmit in parallel a same test data signal to the receiver integrated circuit to determine a performance characteristic of the signaling system, at a time when the victim-line data transmitter is not to transmit the same data signal to the receiver integrated circuit.

9. The transmitter integrated circuit of claim 8 , where each aggressor-line data transmitter comprises a pulse generator to generate a single bit pulse as the same test data signal.

10. The transmitter integrated circuit of claim 9 , where the transmitter integrated circuit is to cause the aggressor-line data transmitters to transmit the same test data signal to the receiver integrated circuit in association with a signaling system operation in which the receiver integrated circuit is to measure a response to the transmitting of the test data signal by the aggressor-line data transmitters on a receiver coupled to the victim transmission line.

11. The transmitter integrated circuit of claim 8 , where the performance characteristic is an electromagnetic coupling effect between the aggressor transmission lines and the victim transmission line.

12. A transmitter integrated circuit for use in a signaling system in which the transmitter integrated circuit is to be coupled to a receiver integrated circuit via transmission lines that form a digital bus, the receiver integrated circuit having at least one receiver to measure a response to transmission of synchronized test signals transmitted by the transmitter integrated circuit, wherein the transmitter integrated circuit comprises:
data transmitters to each transmit data over respective ones of the transmission lines to the receiver integrated circuit;
each of the data transmitters to transmit in parallel one of the synchronized test signals to the receiver integrated circuit, to determine a performance characteristic of the signaling system.

13. The transmitter integrated circuit of claim 12 , where the transmission lines include two aggressor transmission lines and where the transmitter integrated circuit is to be coupled to the receiver integrated circuit also via a victim transmission line of the digital bus, and where the at least one receiver to measure the response includes a victim-line receiver coupled to the victim transmission line.

14. The transmitter integrated circuit of claim 13 , where the transmitter integrated circuit further comprises a processor in the signaling system and where the processor is to cause the synchronized test signals to be transmitted by aggressor-line data transmitters to determine the performance characteristic of the signaling system.

15. The transmitter integrated circuit of claim 12 , where each data transmitter comprises a pulse generator to generate a single bit pulse as a test data signal of the synchronized test signals, and where the synchronized test data signals comprise the single bit pulses of respective ones of the data transmitters, transmitted simultaneously by each of the data transmitters.

16. The transmitter integrated circuit of claim 15 , where the performance characteristic is a characteristic that affects relative transmission of data over the transmission lines.

17. The transmitter integrated circuit of claim 16 , where the performance characteristic is an electromagnetic coupling effect between aggressor transmission lines of the transmission lines of the digital bus and a victim transmission line of the digital bus.

18. The transmitter integrated circuit of claim 15 , where the receiver integrated circuit comprises a receiver for each respective transmission line of the transmission lines, each receiver to measure a single bit response comprising time-varying artifacts from the transmission of the single bit pulse over the respective transmission line.

Assignees

• Rambus Inc

Inventors

• Liaw Haw-Jyh
• Yuan Xingchao
• Horowitz Mark A

Classifications

• H04B17/309

  Measuring or estimating channel quality parameters · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C29/50012

  of timing · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title