Periodic signal measurement using statistical sampling

Patent metadata

Field	Value
Publication number	US-9541591-B2
Application number	US-201514822649-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Aug 11, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.

First claim

The invention claimed is:

1. A method for performing analysis of a periodic signal having an associated duty cycle that is generated in accordance with operations of at least one of a functional circuit and an embedded memory circuit, the method comprising:
performing multiple sampling events during a test period according to a sample timing schedule determined by repeatedly detecting a recurring signal feature of a reference signal, wherein each sampling event of said multiple sampling events includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated sample time determined by detecting an associated said recurring signal feature, and wherein the reference signal has a reference frequency that is uncorrelated to the periodic signal such that each recurring signal feature of said reference signal coincides in time with a substantially random signal phase of said periodic signal, whereby a probability of detecting an asserted state during any given said sampling event is proportional to the associated duty cycle of the periodic signal;
generating a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is in said asserted state; and
generating a second count value including a total number of said plurality of sampling events performed during said test period,
wherein performing said multiple sampling events comprises performing a statistically significant number of said multiple sampling events during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant measurement value of said associated duty cycle of the periodic signal.

2. The method of claim 1 , further comprising generating said reference signal utilizing a reference signal generator circuit configured such that said reference frequency freely floats in accordance with changes in environment conditions of said reference signal generator circuit.

3. The method of claim 1 , wherein generating said reference signal comprises utilizing a ring oscillator configured such that said reference frequency changes in accordance with a temperature of said ring oscillator.

4. The method of claim 1 , wherein performing said plurality of sampling events comprises initiating each said sampling event upon detecting an associated edge of said reference signal.

5. The method of claim 1 , further comprising at least one of storing said first count value and said second count value in memory that is co-disposed on a semiconductor substrate with said at least one of said functional circuit and said embedded memory circuit, and performing on-chip calculation of said ratio using calculating circuitry that is co-disposed on said semiconductor substrate with said at least one of said functional circuit and said embedded memory circuit.

6. The method of claim 5 , further comprising utilizing said calculated ratio of said first count value to said second count value to perform at least one of a phase-locked loop (PLL) clock frequency measurement, an embedded memory delay measurement, a delay corner evaluation, and a process variation evaluation.

7. The method of claim 1 , wherein performing said on-chip analysis comprises:
controlling said embedded memory circuit using a clock signal to generate a repetitive pulse signal by reading alternating “1” and “0” data bit values from memory cells of the embedded memory circuit such that said repetitive pulse signal has a frequency determined by a memory access rate of the embedded memory circuit;
generating a data time delay pulse signal using the repetitive pulse signal and the clock signal;
generating said first count value using said reference signal and said data time delay pulse signal; and
after said test period, calculating a clock-to-output memory access delay time value using the first and second count values.

8. The method of claim 7 , wherein controlling the embedded memory circuit to generate said repetitive pulse signal comprises:
writing a bit pattern into said embedded memory circuit such that each memory cell having an even-numbered memory address stores a “0” bit value, and each memory cell having an odd-numbered memory address stores a “1” bit value; and
reading the bit pattern from the embedded memory circuit by operating the embedded memory circuit in a continuous read operating mode.

9. The method of claim 7 , wherein controlling the embedded memory circuit to generate said repetitive pulse signal comprises:
writing a “0” bit value into a first memory cell and a “1” bit value into a second memory cell; and
repeatedly alternately reading the first and second memory cells.

10. The method of claim 7 , wherein generating the data time delay pulse signal comprises dividing the clock signal by two to generate a half-clock signal, and exclusive-ORing the repetitive pulse signal and the half-clock signal to generate the data time delay pulse signal.

11. The method of claim 7 , wherein calculating the data delay time from memory clock to memory output comprises multiplying the first count value with a period of said periodic signal, dividing by said second count value, and then adding a clock divider flop delay time.

12. An integrated circuit (IC) device comprising:
at least one of a functional circuit and an embedded memory circuit fabricated on a semiconductor substrate and configured to operate in accordance with a system clock signal having a system clock frequency; and
a periodic signal measurement circuit fabricated on the semiconductor substrate and configured to analyze, during a test period, a periodic signal having an associated duty cycle and is generated in accordance with operations of said at least one of said functional circuit and said embedded memory circuit, said periodic signal measurement circuit including:
a reference signal generator configured to generate a reference signal such that a reference frequency of the reference signal is uncorrelated to the periodic signal;
a sampling circuit configured to repeatedly detect a recurring signal feature of said reference signal, and to perform multiple sampling events at respective sample times determined by sequential detections of said recurring signal feature, wherein each sampling event of said multiple sampling events includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated sample time of said respective sample times determined by a detection of an associated recurring signal feature such that a probability of detecting an asserted state during any given said sampling event is proportional to the associated duty cycle of the periodic signal;
a detection counter configured to generate a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is determined to be in said asserted state;
a sampling event counter configured to generate a second count value such that said second count value incrementally increases in response to every said sampling event occurring during said test period; and
a control circuit configured to control said detection counter and said sampling event counter such that a statistically significant number of said multiple sampling events are performed during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant

Assignees

• Synopsys Inc

Inventors

• Darbinyan Karen
• Zorian Yervant
• Kumar Arun
• Mkhoyan Mher

Classifications

• G01R29/0273 Primary

  the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit) · CPC title

• G01R23/02 Primary

  Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/31707

  Test strategies (methods for generation of test sequences G01R31/318371) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title