Amplifier adapted for noise suppression
US-9806677-B2 · Oct 31, 2017 · US
US9559643B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9559643-B2 |
| Application number | US-201414474640-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 2, 2014 |
| Priority date | Oct 29, 2013 |
| Publication date | Jan 31, 2017 |
| Grant date | Jan 31, 2017 |
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An amplifier circuit includes: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; and a synthesizing unit configured to synthesize signals at the third and fourth nodes.
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What is claimed is: 1. An amplifier circuit comprising: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; dipole antennas configured to synthesize signals at the third and fourth nodes in space and output a radio signal; and a first balun circuit configured to convert a single-phase signal to differential signals, and output the differential signals to the first and second nodes. 2. The amplifier circuit according to claim 1 , wherein a number of the plurality of field effect transistors is an even number.
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