Off-chip distributed drain biasing of high power distributed amplifier monolithic microwave integrated circuit (MMIC) chips

Patent metadata

Field	Value
Publication number	US-9673759-B1
Application number	US-201514976427-A
Country	US
Kind code	B1
Filing date	Dec 21, 2015
Priority date	Dec 21, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.

First claim

We claim:

1. A distributed amplifier, comprising:
a distributed amplifier monolithic microwave integrated circuit (MMIC) chip, said chip comprising an RF input configured to receive an RF signal that propagates down an input transmission line, a plurality of parallel-connected FET amplifier stages and an output transmission line that connects the drain terminals of the FET amplifier stages, said FET amplifier stages producing an amplified RF signal over a bandwidth at an RF output of the last FET amplifier stage;
an off-chip bias circuit comprising a common input for receiving a DC bias current from a DC supply and a plurality of parallel-connected bias chokes among which the DC bias current is divided, each bias choke comprising a series inductor L connected to a grounded capacitor C, said series inductor L having sufficient impedance to block RF energy from reaching the common input over the entire bandwidth; and
a plurality of connections that electrically and physical connected the plurality of series inductors L in parallel to a like plurality of the drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line.

2. The distributed amplifier of claim 1 , wherein the bandwidth is at least 120% of a center RF frequency.

3. The distributed amplifier of claim 1 , wherein the input transmission lines have a characteristic impedance Z 0 of approximately 50 ohms.

4. The distributed amplifier of claim 1 , wherein a single bias choke can supply a maximum DC bias current limited by the diameter of a wire that forms the series inductor L, wherein said plurality of parallel-connected bias chokes provide a DC bias current capability greater than said maximum DC bias current of a single bias choke.

5. The distributed amplifier of claim 1 , wherein each said bias choke supplies approximately the same amount of DC bias current.

6. The distributed amplifier of claim 1 , wherein each said series inductor L has an inductance of at least 3 nH.

7. The distributed amplifier of claim 1 , wherein each said series inductor L is a wire-wound inductor.

8. The distributed amplifier of claim 1 , wherein each said FET amplifier stage sees a load impedance at its drain terminal, wherein the inductance values of each series inductor L is configured to modify the load impedance of the FET amplifier stage to which it is connected to approximate a target inductance.

9. The distributed amplifier of claim 1 , wherein at least one of the FET amplifier stages sees a load impedance at its drain terminal that absent the off-chip bias circuit is capacitive over at least the lower end of the bandwidth, wherein said off-chip bias circuit includes one said bias choke that is connected to the drain terminal of that FET amplifier stages, said bias choke's series inductor L providing sufficient inductance to modify the load impedance of the FET amplifier stage such that the load impedance is inductive over the entire bandwidth.

10. The distributed amplifier of claim 1 , wherein a plurality of the FET amplifier stages each see a load impedance at its drain terminal that absent the off-chip bias circuit is capacitive over at least the lower end of the bandwidth, wherein said off-chip bias circuit includes a plurality of said bias chokes that are connected to the drain terminals of those FET amplifier stages, said bias choke's series inductor L providing sufficient inductance to modify the load impedance of the FET amplifier stage such that the load impedance is inductive over the entire bandwidth.

11. The distributed amplifier of claim 10 , wherein all of the FET amplifier stages see a load impedance that is inductive over the entire bandwidth.

12. The distributed amplifier of claim 10 , wherein at least two of the series inductors L have different inductance values.

13. The distributed amplifier of claim 1 , wherein the connections provide negligible inductance compared to the chokes series inductor L, insufficient to block RF energy over the bandwidth absent the off-chip series inductor L.

14. A distributed amplifier, comprising:
a distributed amplifier monolithic microwave integrated circuit (MMIC) chip, said chip comprising an RF input configured to receive an RF signal that propagates down an input transmission line, a plurality of parallel-connected FET amplifier stages and an output transmission line that connects the drain terminals of the FET amplifier stages, said FET amplifier stages producing an amplified RF signal over a bandwidth at an RF output of the last FET amplifier stage, at least one said amplifier stage seeing a load impedance at its drain terminal that is capacitive over at least the lower end of the bandwidth;
an off-chip bias circuit comprising a common input for receiving a DC bias current from a DC supply and a plurality of parallel-connected bias chokes among which the DC bias current is divided, each bias choke comprising a series inductor L connected to a grounded capacitor C, said series inductor L having sufficient impedance to block RF energy from reaching the common input over the entire bandwidth; and
a plurality of connections that electrically and physical connected the plurality of series inductors L in parallel to a like plurality of the drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line,
wherein one of said plurality of bias chokes is connected to each of the at least one said amplifier stages that see a capacitive load impedance, said series inductors L providing sufficient inductance to modify the load impedance of the FET amplifier stage such that the load impedance is inductive over the entire bandwidth.

15. A method of off-chip biasing of a amplifier monolithic microwave integrated circuit (MMIC) chip, said chip comprising an RF input configured to receive an RF signal that propagates down an input transmission line, a plurality of parallel-connected FET amplifier stages and an output transmission line that connects the drain terminals of the FET amplifier stages, said FET amplifier stages producing an amplified RF signal over a bandwidth at an RF output of the last FET amplifier stage, said method comprising:
providing an off-chip bias circuit comprising a common input and a plurality of parallel-connected bias chokes, each bias choke comprising a series inductor L connected to a grounded capacitor C;
connecting the common input to a DC supply to draw a DC bias current;
connecting the plurality of series inductors L in parallel to a like plurality of the drain terminals at different FET amplifier stages to divide the DC bias current among the bias chokes and supply portions of the DC bias current at different locations along the output transmission line,
wherein said series inductor L has sufficient impedance to block RF energy from reaching the common input over the entire bandwidth.

16. The method of claim 15 , wherein a single bias choke can supply a maximum DC bias current limited by the diameter of a wire that forms the series inductor L, wherein said plurality of parallel-connected bias chokes provide a DC bias current capability greater than said maximum DC bias current.

17. The method of claim 15 , wherein absent the off-chip bias circuit at least one said amplifier stage sees a load impedance at its drain terminal that is capacitive over at least the lower end of the bandwidth, wherein one of said plurality of bias chokes is connected to each of the at least one said amplifier stages that see a capacitive load impedance,

Assignees

• Raytheon Co

Inventors

• Fletcher David R
• Heston David D

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W44/231

  Arrangements for applying bias · CPC title

• H10W44/206

  Wires · CPC title

• H10W44/20 Primary

  at high-frequency [HF] or radio frequency [RF] · CPC title