Self-limited crack etch to prevent device shorting

Patent metadata

Field	Value
Publication number	US-9559292-B2
Application number	US-201615070436-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Feb 24, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer. A self-limiting second trench extends through the hardmask layer and the piezoelectric layer without reaching the first metal layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a starting substrate including a piezoelectric layer interposed between a first metal layer and a hardmask layer;
performing a patterning process that forms at least one isolated pattern and a guard trench in the hardmask such that the guard trench surrounds the at least one isolated pattern; and
performing an etching process that transfers the isolated pattern and the guard trench into the starting substrate such that the guard trench protects the at least one isolated pattern from re-sputtered metal.

2. The method of claim 1 , wherein performing the patterning process further comprises forming the guard trench to have a first size that is greater than a second size of the at least one isolated pattern.

3. The method of claim 2 , wherein the first size induces a faster etching rate than the second size.

4. The method of claim 2 , wherein performing the etching process transfers the guard trench through the first metal layer while the at least one isolated pattern self-limits at the piezoelectric layer without reaching the first metal layer.

5. The method of claim 4 , wherein sidewalls of the guard trench capture re-sputtered metal of the first metal layer so as to protect the at least one isolated pattern.

6. The method of claim 1 , wherein the first patterning process includes a reactive ion etch process.

7. The method of claim 3 , wherein a depth at which the at least one isolated pattern self-limits is based on the second size.

8. The method of claim 4 , wherein the etching process is a single reactive ion etching process that simultaneously transfers the guard trench through the first metal layer while the at least one isolated pattern self-limits at the piezoelectric layer.

9. The method of claim 1 , wherein forming the starting substrate further includes forming the first metal layer on a substrate base and interposing a second metal layer between the piezoelectric layer and the hardmask layer.

10. The method of claim 9 , further comprising selectively patterning the hardmask layer such that the guard trench and the at least one isolated pattern stop on an upper surface of the second metal layer after completing the patterning process.

11. The method of claim 10 , further comprising transferring the guard trench and the at least one isolated pattern through the second metal layer using the etching process, wherein the guard trench is transferred through the first metal layer to expose the substrate base.

12. The method of claim 11 , wherein the first metal layer is a metal gate layer comprising an electrically conductive metal material.

13. The method of claim 12 , wherein the metal gate layer comprises platinum (Pt).

14. The method of claim 13 , further comprising forming electrically conductive sidewalls on the inner walls of the guard trench to electrically connect the metal gate layer to the second metal layer.

15. The method of claim 1 , wherein the at least one isolated pattern defines a first piezoelectric transistor (PET), and the guard trench electrically isolates the first PET from neighboring PETs formed in the starting substrate.

Assignees

• IBM

Inventors

• Bryce Brian A
• Chang Josephine B
• Miyazoe Hiroyuki

Classifications

• H10P50/267

  using plasmas · CPC title

• H01L41/0471

  Electricity · mapped topic

• H01L41/332 Primary

  Electricity · mapped topic

• H01L41/0477

  Electricity · mapped topic

• H01L29/84

  Electricity · mapped topic