On-chip combined hot carrier injection and bias temperature instability monitor
US-2016377672-A1 · Dec 29, 2016 · US
US9557369B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9557369-B2 |
| Application number | US-201213530782-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 22, 2012 |
| Priority date | Jun 22, 2012 |
| Publication date | Jan 31, 2017 |
| Grant date | Jan 31, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
Opening claim text (preview).
What is claimed is: 1. A method for reliability testing, comprising: applying a stress to a device under test (DUT); measuring an electrical characteristic of the DUT; triggering measurement of an optical characteristic of the DUT based on a timing of the measurement of the electrical characteristic; and correlating the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions. 2. The method of claim 1 , wherein correlating includes convolving a vector formed from leakage current measurements with a vector formed from optical emission measurements. 3. The method of claim 2 , wherein correlating includes calculating the maximum value of the convolution as Corr = max ( ∑ j E ( j ) I ( k + 1 - j ) ) , where k=1, . . . , m+n−1, m is the number of electrical measurements, n is a number of optical measurements, E is the optical measurement vector, and I is the electrical measurement vector. 4. The method of claim 1 , wherein the electrical measurement is repeated periodically. 5. The method of claim 1 , further comprising halting said stress, electrical measurement, and optical measurement, based on said correlating. 6. The method of claim 1 , wherein correlating further comprises segmenting an image of the DUT and determining a maximum emission intensity for each segment to localize emissions. 7. A method for reliability testing, comprising: applying a stress voltage to a device under test (DUT); periodically measuring a leakage current across the DUT to form an electrical measurement vector; triggering measurement of optical emissions from the DUT based on the timing of the measurement of leakage current, and correlating the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by: segmenting an image of the DUT and determining a maximum emission intensity for each segment to localize emissions and form an optical emission measurement vector; convolving the electrical measurement vector with the optical measurement vector to form a convolved vector; and determining the maximum value in the convolved vector.
related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title
Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title
Environmental, reliability or burn-in testing · CPC title
of integrated circuits {(G01R31/31728 takes precedence)} · CPC title
Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing (G01R31/2818 takes precedence) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.