On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures

Patent metadata

Field	Value
Publication number	US-9553348-B2
Application number	US-201615097648-A
Country	US
Kind code	B2
Filing date	Apr 13, 2016
Priority date	Aug 23, 2013
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.

First claim

What is claimed is:

1. A method, comprising:
forming a first microstrip line structure comprising a ground plate within a back end of the line (BEOL) stack; and
forming a second microstrip line structure comprising a signal line separated from the BEOL stack by a predetermined horizontal distance,
forming a first metal strip below the ground plate and a second metal strip below the signal line such that the first metal strip is formed in a different horizontal plane than the second metal strip, wherein:
the ground plate is formed on a first vertical plane that intersects the BEOL stack and in a portion of an oxide layer of the BEOL stack;
the signal line is formed on a second vertical plane that avoids intersecting the BEOL stack and in a portion of another oxide layer that is separated from the BEOL stack, and
the oxide layer of the BEOL stack is different from the another oxide layer that is separated from the BEOL stack.

2. The method of claim 1 , wherein:
the ground plate is formed symmetrical along the first vertical plane that intersects the BEOL stack; and
the signal line is formed symmetrical along the second vertical plane that avoids intersecting the BEOL stack.

3. The method of claim 1 , wherein the BEOL stack is over a substrate, the first vertical plane is parallel to the second vertical plane, and the first vertical plane and the second vertical plane are perpendicular to a top surface of the substrate.

4. The method of claim 1 , wherein the predetermined horizontal distance from the BEOL stack is selected to achieve a predetermined impedance.

5. The method of claim 4 , wherein the predetermined horizontal distance is about 2-4 μm.

6. The method of claim 1 , wherein the second microstrip line structure is formed with a predetermined width that is selected to achieve a predetermined impedance.

7. The method of claim 1 , wherein the first microstrip line structure and the second microstrip line structure are formed using complementary metal oxide semiconductor (CMOS) technology.

8. A structure, comprising:
a back end of the line (BEOL) stack comprising a plurality of metallization layers and a plurality of dielectric layers;
a first microstrip line structure comprising a ground plate on a first vertical plane that intersects the BEOL stack and formed in a portion of an oxide layer of the dielectric layers of the BEOL stack;
a second microstrip line structure comprising a signal line on a second vertical plane that avoids intersecting the BEOL stack, the second vertical plane being at a predetermined horizontal distance from the BEOL stack and being formed in a portion of another oxide layer different than the dielectric layers, that is separated from the BEOL stack;
a first metal strip formed below the ground plate; and
a second metal strip formed below the signal line and in a different horizontal plane than the first metal strip.

9. The structure of claim 8 , further comprising a substrate, wherein the BEOL stack is over the substrate, the first vertical plane is parallel to the second vertical plane, and the first vertical plane and the second vertical plane are perpendicular to a top surface of the substrate.

10. The structure of claim 8 , wherein:
the first microstrip line structure is symmetrical along the first vertical plane that intersects the BEOL stack; and
the second microstrip line structure is symmetrical along the second vertical plane that avoids intersecting the BEOL stack.

11. The structure of claim 8 , wherein the second microstrip line structure has a predetermined width that is selected to achieve a predetermined impedance.

12. The structure of claim 8 , wherein the predetermined horizontal distance is about 2-4 μm.

Assignees

• IBM

Inventors

• Dewitt Barbara S
• Mina Essam
• Rahman Bm Farid
• Wang Guoan

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H01P3/082

  Multilayer dielectric · CPC title