On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures

Patent metadata

Field	Value
Publication number	US-9362606-B2
Application number	US-201313974804-A
Country	US
Kind code	B2
Filing date	Aug 23, 2013
Priority date	Aug 23, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.

First claim

What is claimed is:

1. A method, comprising:
forming a first microstrip line structure comprising a ground plate within a back end of the line (BEOL) stack; and
forming a second microstrip line structure comprising a signal line separated from the BEOL stack by a predetermined horizontal distance,
wherein the ground plate is formed on a first vertical plane that runs through the BEOL stack and the signal line is formed on a second vertical plane that runs outside the confines of the BEOL stack,
wherein a metal strip is formed below the ground plate and the signal line to further minimize insertion loss due to substrate coupling,
wherein the metal strip intersects the first vertical plane and the second vertical plane, and a dielectric material is between and contacts both the signal line and a portion of the metal strip that intersects the second vertical plane,
wherein layers of the BEOL stack are devoid of any gap between each layer of the BEOL stack,
wherein the ground plate is formed as a part of a lower metallization layer in a portion of an oxide layer of the BEOL stack, and the signal line is formed in a portion of another oxide layer that is separated from the BEOL stack by the dielectric material, and
wherein the oxide layer of the BEOL stack is different from the another oxide layer that is separated from the BEOL stack.

2. The method of claim 1 , wherein the ground plate is formed in a first dielectric layer and the signal line is formed in a second dielectric layer.

3. The method of claim 2 , wherein:
the first vertical plane is parallel to the second vertical plane, and the first vertical plane and the second vertical plane are perpendicular to a top surface of a substrate.

4. The method of claim 1 , wherein:
the ground plate is formed symmetrical along the first vertical plane that runs through the BEOL stack; and
the signal line is formed symmetrical along the second vertical plane that runs outside the confines of the BEOL stack.

5. The method of claim 1 , wherein the predetermined horizontal distance from the BEOL stack is selected to achieve a predetermined impedance.

6. The method of claim 5 , wherein the predetermined horizontal distance is about 24 μM.

7. The method of claim 1 , wherein the second microstrip line structure is formed with a predetermined width that is selected to achieve a predetermined impedance.

8. The method of claim 1 , wherein the first microstrip line structure and the second microstrip line structure are formed using complementary metal oxide semiconductor (CMOS) technology.

9. The method of claim 1 , wherein the metal strip is copper and is formed using a damascene process.

10. The method of claim 1 , wherein the metal strip comprises a first metal strip which contacts the ground plate in the first vertical plane and a second metal strip which contacts the signal line in the second vertical plane, and the first metal strip and the same metal strip are formed in a same horizontal plane.

11. A structure, comprising:
a back end of the line (BEOL) stack comprising a plurality of metallization layers and a plurality of dielectric layers;
a first microstrip line structure comprising a ground plate on a first vertical plane that runs through the BEOL stack; and
a second microstrip line structure comprising a signal line on a second vertical plane that runs outside the confines of the BEOL stack,
wherein the second vertical plane is at a predetermined horizontal distance from the BEOL stack,
wherein a metal strip is formed below the ground plate and the signal line to further minimize insertion loss due to substrate coupling,
wherein the metal strip intersects the first vertical plane and the second vertical plane, and a dielectric material is between and contacts both the signal line and a portion of the metal strip that intersects the second vertical plane,
wherein layers of the BEOL stack are devoid of any gap between each layer of the BEOL stack,
wherein the ground plate is formed as a part of a lower metallization layer of the metallization layer in a portion oxide layer of the BEOL stack, and the signal line is formed in a portion of another oxide layer that is separated from the BEOL stack by the dielectric material, and
wherein the oxide layer of the BEOL stack is different from the another oxide layer that is separated from the BEOL stack.

12. The structure of claim 11 , wherein:
the ground plate is formed in the plurality of dielectric layers;
the signal line is formed in a second dielectric layer.

13. The structure of claim 11 , further comprising a substrate, wherein:
the BEOL stack is over the substrate, the first vertical plane is parallel to the second vertical plane, and the first vertical plane and the second vertical plane are perpendicular to a top surface of the substrate.

14. The structure of claim 11 , wherein:
the first microstrip line structure is symmetrical along the first vertical plane that runs through the BEOL stack; and
the second microstrip line structure is symmetrical along the second vertical plane that runs outside the confines of the BEOL stack.

15. The structure of claim 11 , wherein the predetermined horizontal distance is about 2-4μm.

16. The structure of claim 11 , wherein the second microstrip line structure has a predetermined width that is selected to achieve a predetermined impedance.

17. A design structure readable by a machine used in design, manufacture, or simulation of an integrated circuit, the design structure being implemented in the machine and being representative of the integrated circuit, comprising:
a back end of the line (BEOL) stack comprising a plurality of metallization layers and a plurality of dielectric layers;
a first microstrip line structure comprising a ground plate on a first vertical plane that runs through the BEOL stack; and
a second microstrip line structure comprising a signal line on a second vertical plane that runs outside the confines of the BEOL stack,
wherein the second vertical plane is at a predetermined horizontal distance from the BEOL stack,
wherein a metal strip is formed below the ground plate and the signal line to further minimize insertion loss due to substrate coupling,
wherein the metal strip intersects the first vertical plane and the second vertical plane, and a dielectric material is between and contacts both the signal line and a portion of the metal strip that intersects the second vertical plane,
wherein layers of the BEOL stack are devoid of any gap between each layer of the BEOL stack,
wherein the ground plate is formed as a part of a lower metallization layer of the metallization layer in a portion of an oxide layer of the BEOL stack, and the sigma line is formed in a portion of another oxide layer that is separated from the BEOL stack by the dielectric material, and
wherein the oxide layer of t e BEOL stack is different from the another oxide layer that is separated from the BEOL stack.

18. The design structure of claim 17 , wherein:
the ground plate is formed in the plurality of dielectric layers;
and the signal line is formed in a second dielectric layer.

19. The design structure of claim 17 , wherein the design structure comprises a netlist.

20. The design structure of claim 17 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits or in a programmable gate array.

Assignees

• IBM
• Univ South Carolina
• Univeristy Of South Carolina

Inventors

• Dewitt Barbara S
• Mina Essam
• Rahman B M Farid
• Wang Guoan

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H01P11/003

  Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title