Recessed and embedded die coreless package

Patent metadata

Field	Value
Publication number	US-9553075-B2
Application number	US-201514831250-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Dec 29, 2009
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

First claim

What is claimed is:

1. A structure, comprising:
a partially embedded die disposed in a coreless substrate, wherein the partially embedded die includes a top surface and a bottom/active surface;
wherein the coreless substrate includes a dielectric material having a planar top portion, wherein the partially embedded die bottom/active resides within the dielectric material below the dielectric material planar top portion of the coreless substrate, and wherein the partially embedded die top surface does not contact the coreless substrate; and
raised PoP lands adjacent the partially embedded die on the dielectric material planar top portion of the coreless substrate.

2. The structure of claim 1 further comprising an adhesive film disposed on a top surface of the partially embedded die, and wherein the coreless substrate comprises a portion of a POP package structure.

3. The structure of claim 1 wherein the coreless substrate comprises a portion of a PoP package structure, and further wherein interconnect structures of a second package are disposed on the PoP lands of the coreless substrate.

4. The structure of claim 3 wherein a die of the second package is directly above the partially embedded die disposed in the coreless substrate.

5. The structure of claim 1 wherein there is a distance between a top side of the die and a top side of the PoP land.

6. A structure comprising:
a die disposed in a coreless substrate, wherein at least a portion of the die is embedded in the coreless substrate and wherein the die includes a top surface and a bottom/active surface;
wherein the coreless substrate includes a dielectric material having a planar top portion, wherein the partially embedded die bottom/active resides within the dielectric material below the dielectric material planar top portion of the coreless substrate, and wherein the partially embedded die top surface does not contact the coreless substrate;
raised PoP lands adjacent the die on the dielectric material planar top portion of the coreless substrate, wherein the PoP lands and the die are capable of receiving a second substrate;
a dielectric film adjacent the die bottom/active surface, wherein die interconnect structures are disposed in the dielectric film and are connected to pads of the die bottom/active surface;
PoP interconnect structures that are connected to the PoP lands; and
a first metal layer disposed on the PoP interconnect structures and on the die interconnect structures.

7. The structure of claim 6 wherein the PoP lands comprise plated metal.

8. The structure of claim 6 wherein the coreless substrate comprises a portion of coreless package structure, wherein a second package is connected to the coreless package structure.

9. The structure of claim 8 wherein interconnect structures of the second package are connected to the PoP lands of the coreless package structure.

10. The structure of claim 6 wherein the die comprises a thickness of less than about 150 microns.

11. The structure of claim 6 further comprising a system comprising: a bus communicatively coupled to the structure; and a DRAM communicatively coupled to the bus.

12. A structure comprising:
a die having a thickness of less than about 150 microns disposed in a coreless substrate, wherein at least a portion of the die is embedded in the coreless substrate-and wherein the die includes a top surface and a bottom/active surface;
wherein the coreless substrate includes a dielectric material having a planar top portion, wherein the partially embedded die bottom/active resides within the dielectric material below the dielectric material planar top portion of the coreless substrate, and wherein the partially embedded die top surface does not contact the coreless substrate;
raised PoP lands comprising a plated metal adjacent the die on the dielectric material planar top portion of the coreless substrate;
a dielectric film adjacent the die bottom/active surface, wherein die interconnect structures are disposed in the dielectric film and are connected to pads of the die bottom/active surface;
PoP interconnect structures that are connected to the PoP lands;
a first metal layer disposed on the PoP interconnect structures and on the die interconnect structures;
wherein the coreless substrate comprises a portion of coreless package structure; and
a second package connected to the coreless package structure, wherein the second package is connected to the PoP lands of the coreless package structure with PoP interconnect structure solder balls.

Assignees

• Intel Corp

Inventors

• Guzek John

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9413

  on encapsulations · CPC title