Bias circuit for a transistor amplifier

Patent metadata

Field	Value
Publication number	US-9548701-B2
Application number	US-201514635616-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Mar 17, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein
the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.

First claim

The invention claimed is:

1. A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein
the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor;
the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node;
the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and
the current difference block includes a gate, a first current electrode, and a second current electrode, and is configured to receive the difference current from the sum node at the first current electrode and provide the difference current at the second current electrode to the control terminal of the transistor amplifier.

2. The bias circuit of claim 1 , wherein the bias circuit comprises a current compensation block configured to receive the bias current from the reference transistor and return a control current to the control terminal of the reference transistor.

3. The bias circuit of claim 2 , wherein the current compensation block comprises a cascode transistor and a first current compensation mirror, and wherein the first current compensation mirror is configured to mirror a control current of the cascode transistor and provide a mirrored control current to the control terminal of the reference transistor.

4. The bias circuit of claim 3 , wherein the current compensation block comprises a second current compensation mirror configured to provide the mirrored control current to the control terminal of the transistor amplifier.

5. The bias circuit of claim 4 , wherein the second current compensation mirror is configured to provide the mirrored control current to the control terminal of the transistor amplifier via the current difference block.

6. The bias circuit of claim 4 , wherein the size ratio of the first current compensation mirror to the second current compensation mirror is substantially the same as the size ratio of the reference transistor to the transistor amplifier.

7. The bias circuit claim 2 , wherein the bias circuit comprises a reference current mirror configured to receive a reference current and provide a scaled copy of the reference current to the sum node, and wherein the sum node is configured to combine the scaled copy of the reference current with the bias current from the reference transistor to provide the difference current.

8. The bias circuit of claim 7 , wherein the reference current mirror is configured to receive an additional current from the current compensation block and provide a scaled copy of the reference and additional currents to the sum node, and wherein the sum node is configured to combine the scaled copy of the reference and additional currents with the bias current from the reference transistor to provide the difference current.

9. The bias circuit of claim 7 , wherein the reference current mirror comprises a pair of transistors, and wherein the bias circuit comprises a voltage shift transistor configured to provide a control current to control terminals of the transistors of the reference current mirror.

10. The bias circuit of claim 9 , wherein the current difference block comprises a current difference cascode transistor, and wherein the voltage shift transistor is configured to provide a control voltage to a control terminal of the current difference cascode transistor.

11. The bias circuit of claim 7 , wherein the bias circuit comprises a voltage supply terminal, and wherein the current compensation block and the reference current mirror are connected to the voltage supply terminal independently of one another.

12. The bias circuit of claim 1 , wherein the current difference block comprises a current difference transistor and a current difference mirror, the current difference mirror configured to amplify an output current of the current difference transistor.

13. The bias circuit of claim 12 , wherein the current difference block comprises a diode-connected transistor configured to provide an increased input voltage to the current difference transistor.

14. The bias circuit of claim 1 , wherein the low-pass filter block comprises one or more resistor-capacitor circuits.

15. A transistor amplifier circuit comprising a transistor amplifier and the bias circuit of claim 1 .

16. A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein
the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor;
the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node;
the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and
the current difference block is configured to receive the difference current from the sum node and transfer the difference current to the control terminal of the transistor amplifier, wherein the current difference block provides unity gain.

17. The bias circuit of claim 16 , wherein the bias circuit comprises a current compensation block configured to receive the bias current from the reference transistor and return a control current to the control terminal of the reference transistor.

18. The bias circuit of claim 17 , wherein the current compensation block comprises a cascode transistor and a first current compensation mirror, and wherein the first current compensation mirror is configured to mirror a control current of the cascode transistor and provide a mirrored control current to the control terminal of the reference transistor.

19. The bias circuit of claim 18 , wherein the current compensation block comprises a second current compensation mirror configured to provide the mirrored control current to the control terminal of the transistor amplifier.

20. A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein
the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor;
the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node;
the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and
the current difference block is configured to receive the difference current from the sum node and transfer the difference current without amplification to the control terminal of the transistor amplifier.

Assignees

• Ridgers Timothy John
• Praamsma Louis
• Nxp Bv

Inventors

• Ridgers Timothy John
• Praamsma Louis

Classifications

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F2200/456

  A scaled replica of a transistor being present in an amplifier · CPC title

• H03F2200/447

  the amplifier being protected to temperature influence · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title