Array substrate and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9548324-B2
Application number	US-201414430310-A
Country	US
Kind code	B2
Filing date	May 12, 2014
Priority date	Dec 27, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate ( 20 ), a first metal layer including patterns of gate electrodes ( 21, 24 ) of a first and second TFTs, an active layer ( 27 ) and a gate insulation layer ( 28 ) are formed on the substrate; forming an etch stop layer film and a photoresist sequentially on the substrate ( 20 ), and allowing the photoresist to form a first, second and third regions through gray-scale exposing and developing; forming a pattern of an etch stop layer ( 29 ), a connection via hole ( 30 ), and a contact via hole ( 31 ) respectively in the first, second and third regions through a patterning process; and forming source electrodes and drain electrodes ( 22, 23,25, 26 ) of the first and second TFTs. Photoresist of different thicknesses are disposed according to etch depths, thereby avoiding the over-etch of relatively shallow via holes.

First claim

What is claimed is:

1. A method for fabricating an array substrate, comprising:
providing a substrate, wherein a first metal layer, a gate insulation layer and an active layer are formed on the substrate, and the first metal layer comprises patterns of a gate electrode of a first TFT and a gate electrode of a second TFT;
forming an etch stop layer film on the substrate;
applying a photoresist to the etch stop layer film, gray-scale exposing and developing the photoresist to form a first region having a first thickness, a second region having a second thickness and a third region having a third thickness, wherein the first thickness, the second thickness and the third thickness are not equal to each other, and the first thickness is larger than the second and third thicknesses;
forming, through a patterning process, a pattern of an etch stop layer in the first region, a connection via hole for connecting a drain electrode of the first TFT to the gate electrode of the second TFT in the second region, and a contact via hole for connecting respective source electrode and drain electrode of each of the first and second TFTs to the active layer in the third region; and
forming a second metal layer film on the substrate done with the previous steps, forming a source electrode and a drain electrode of the first TFT, as well as a source electrode and a drain electrode of the second TFT through a patterning process, wherein the source electrode and the drain electrode of each of the first and second TFTs are respectively electrically connected to the active layer by way of the contact via hole, and the drain electrode of the first TFT is electrically connected to the gate electrode of the second TFT by way of the connection via hole; wherein both the first TFT and the second TFT are top-gate TFTs.

2. The method of claim 1 , wherein the formation of the first metal layer, the gate insulation layer and the active layer comprises:
forming an active layer film on the provided substrate, and forming a pattern comprising the active layer through a patterning process;
forming the gate insulation layer on the substrate done with the previous step; and
forming a first metal film on the substrate done with the previous step, and forming a pattern of a gate electrode metal layer comprising the gate electrode of the first TFT and that of the second TFT through a patterning process.

3. The method of claim 1 , wherein the second thickness is larger than the third thickness.

4. The method of claim 3 , wherein the third thickness is zero.

5. The method of claim 1 , wherein the step of gray-scale exposing and developing the photoresist to form a first region having a first thickness, a second region having a second thickness and a third region having a third thickness comprises:
exposing the photoresist to form the first region, the second region and the third region by utilizing a gray-scale exposing light source, or a plurality of light sources with different exposure intensities, or a plurality of masks.

6. The method of claim 1 , wherein the pattern of the etch stop layer is formed from the etch stop layer film under the first region.

7. The method of claim 1 , wherein the connection via hole is formed in the etch stop layer film under the second region and penetrates through the etch stop layer film.

8. The method of claim 1 , wherein the contact via hole is formed in the etch stop layer film and the gate insulation layer under the third region and penetrates through the etch stop layer film and the gate insulation layer.

9. The method of claim 2 , wherein the second thickness is larger than the third thickness.

10. The method of claim 9 , wherein the third thickness is zero.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Yanzhao
• Wang Gang
• Wang Dongfang
• Liu Wei
• Fang Jingang

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H01L21/0274

  Electricity · mapped topic

• H01L27/1288 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic