Semiconductor devices including a dummy gate structure on a fin

Patent metadata

Field	Value
Publication number	US-9548309-B2
Application number	US-201615047181-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	May 8, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a first region and a second region;
a first fin protruding from the substrate and extending in a first direction on the first region;
a recess extending in a second direction different from the first direction in the first fin;
a dummy gate structure overlapping the recess and extending in the second direction;
second and third fins on the second region, protruding from the substrate, and extending in the first direction; and
a trench between the second fin and the third fin such that the second fin and the third fin are spaced apart from each other,
wherein a height and a width of the recess are smaller than those of the trench.

2. The semiconductor device of claim 1 , wherein the height of the recess is smaller than that of the fin and the height of the trench is greater than that of the fin.

3. The semiconductor device of claim 1 , further comprising a first device isolation layer filling the recess and a second device isolation layer filling the trench.

4. The semiconductor device of claim 3 , further comprising a capping layer between the recess and the first device isolation layer which is conformally formed along an inner surface of the recess.

5. The semiconductor device of claim 3 , wherein the second device isolation layer include the same material as the first device isolation layer.

6. The semiconductor device of claim 1 , wherein the first region is a memory region and the second region is a core/periphery region.

7. The semiconductor device of claim 1 , wherein the first region is a Static Random Access Memory (SRAM) region and the second region is a logic region.

Assignees

• Park Sang-Jine
• Kwon Kee-Sang
• Kim Do-Hyoung
• Yoon Bo-Un
• Bai Keun-Hee
• Yang Kwang-Yong
• Yeo Kyoung-Hwan
• Jeon Yong-Ho
• Samsung Electronics Co Ltd

Inventors

• Park Sang-Jine
• Kwon Kee-Sang
• Kim Do-Hyoung
• Yoon Bo-Un
• Bai Keun-Hee
• Yang Kwang-Yong
• Yeo Kyoung-Hwan
• Jeon Yong-Ho

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title