Structure and formation method of finfet device

Patent metadata

Field	Value
Publication number	US-2016190243-A1
Application number	US-201414582975-A
Country	US
Kind code	A1
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure and a source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device structure further includes an isolation layer between the source/drain structure and the semiconductor substrate.

First claim

1 . A semiconductor device structure, comprising:
a semiconductor substrate; a fin structure over the semiconductor substrate; a gate stack covering a portion of the fin structure; a source/drain structure over the fin structure and adjacent to the gate stack; and an isolation layer between the source/drain structure and the semiconductor substrate., wherein the isolation layer is directly under the source/drain structure.

2 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer is between the source/drain structure and the fin structure.

3 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer is in direct contact with the source/drain structure.

4 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer is in direct contact with the fin structure.

5 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer is made of silicon germanium oxide.

6 . The semiconductor device structure as claimed in claim 1 , further comprising a semiconductor material layer between the isolation layer and the source/drain structure.

7 . The semiconductor device structure as claimed in claim 6 , wherein the source/drain structure has an atomic concentration of germanium greater than that of the semiconductor material layer.

8 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer has a bottom surface curved towards the source/drain structure.

9 . The semiconductor device structure as claimed in claim 1 , further comprising a second fin structure between the fin structure and the semiconductor substrate, wherein materials of the fin structure and the second fin structure are different from each other.

10 . The semiconductor device structure as claimed in claim 9 , further comprising a second isolation layer between the fin structure and the second fin structure, wherein the second isolation layer is in direct contact with the second fin structure and the first fin structure.

11 . A semiconductor device structure, comprising:
a semiconductor substrate; a fin structure over the semiconductor substrate; a germanium-containing fin structure over the fin structure; a gate stack covering a portion of the germanium-containing fin structure; a source/drain structure over the germanium-containing fin structure and adjacent to the gate stack; and an isolation layer between the source/drain structure and the semiconductor substrate, wherein the isolation layer is directly under the source/drain structure.

12 . The semiconductor device structure as claimed in claim 11 , wherein the isolation layer is between the source/drain structure and the germanium-containing fin structure.

13 . The semiconductor device structure as claimed in claim 12 , further comprising a second isolation layer between the fin structure and the germanium-containing fin structure.

14 . The semiconductor device structure as claimed in claim 11 , wherein the isolation layer is between the fin structure and the germanium-containing fin structure.

15 . The semiconductor device structure as claimed in claim 11 , wherein a portion of the source/drain structure extends into the fin structure.

16 - 20 . (canceled)

21 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer has a V-shaped profile.

22 . The semiconductor device structure as claimed in claim 1 , wherein the isolation layer has a top surface curved towards the fin structure under the isolation layer.

23 . The semiconductor device structure as claimed in claim 11 , further comprising a semiconductor material layer between the isolation layer and the source/drain structure.

24 . The semiconductor device structure as claimed in claim 23 , wherein the source/drain structure has an atomic concentration of germanium greater than that of the semiconductor material layer.

25 . The semiconductor device structure as claimed in claim 1 , further comprising a recess formed above the fin structure, wherein a portion of the isolation layer is disposed on a sidewall of the recess.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Tung-Ying
• Huang Yu-Lien

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/795

  being in lateral device isolation regions, e.g. STI · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6215 Primary

  having multiple independently-addressable gate electrodes · CPC title