Integrated circuit die decoupling system with reduced inductance

Patent metadata

Field	Value
Publication number	US-9548288-B1
Application number	US-201514966482-A
Country	US
Kind code	B1
Filing date	Dec 11, 2015
Priority date	Dec 22, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.

First claim

What is claimed is:

1. A system, comprising:
an integrated circuit die including:
a plurality of circuits, wherein each circuit of the plurality of circuits includes a plurality of devices interconnected by a first plurality of wires fabricated on a first plurality of conductive layers; and
wherein a first circuit of the plurality of circuits includes and an Input/Output (I/O) terminal; and
wherein a second circuit of the plurality of circuits includes a plurality of power terminals;
an interconnection region including:
a plurality of conductive paths, wherein each conductive path of the plurality of conductive paths includes a second plurality of wires fabricated on a second plurality of conductive layers;
a plurality of solder balls, wherein at least one solder ball of the plurality of solder balls is coupled to the I/O terminal of the first circuit by a first conductive path of the plurality of conductive paths;

at least one decoupling unit including a plurality of capacitors and a plurality of terminals, wherein each terminal of the plurality of terminals is coupled to a respective one the plurality of power terminals of the second circuit via a respective one of a subset of the plurality of conductive paths.

2. The system of claim 1 , wherein each capacitor of the plurality of capacitors comprises a trench capacitor.

3. The system of claim 1 , wherein each capacitor of the plurality of capacitors comprises a Metal Insulator Metal (MIM) capacitor.

4. The system of claim 1 , wherein a direction of current flow through a first capacitor of the plurality of capacitors is opposite of a direction of current flow through a second capacitor of the plurality of capacitors.

5. The system of claim 1 , wherein each terminal of a first subset of the plurality of power terminals is coupled to a positive power supply node included in the second circuit, and wherein each terminal of a second subset of the plurality of power terminals is coupled to a ground node included in the second circuit.

6. The system of claim 1 , wherein the at least one decoupling unit further includes an inductor.

7. The system of claim 1 , wherein the at least one decoupling unit includes at least one resistor.

8. The system of claim 7 , wherein the at least one resistor is coupled in series with at least one capacitor of the plurality of capacitors.

9. The system of claim 7 , wherein the at least one resistor is coupled in parallel with at least one capacitor of the plurality of capacitors.

10. A system, comprising:
a processor;
a memory interconnect to the processor by a first plurality of wires fabricated on a first plurality of conductive layers, wherein the memory includes a plurality of power terminals;
an interconnection region including a plurality of conductive paths, wherein each conductive path of the plurality of conductive paths includes a second plurality of wires fabricated on a second plurality of conductive layers; and
at least one decoupling unit including a plurality of capacitors and a plurality of terminals, wherein each terminal of the plurality of terminals is coupled to a respective one the plurality of power terminals of the memory via a respective one of a subset of the plurality of conductive paths.

11. The system of claim 10 , wherein at least one capacitor of the plurality of capacitors comprises a trench capacitor.

12. The system of claim 10 , wherein at least one capacitor of the plurality of capacitors comprises a Metal Insulator Metal (MIM) capacitor.

13. The system of claim 10 , wherein a direction of current flow through a first capacitor of the plurality of capacitors is opposite of a direction of current flow through a second capacitor of the plurality of capacitors.

14. The system of claim 10 , wherein each terminal of a first subset of the plurality of power terminals is coupled to a positive power supply node included in the memory, and wherein each terminal of a second subset of the plurality of power terminals is coupled to a ground node included in the memory.

15. The system of claim 10 , wherein the at least one decoupling unit includes at least one resistor.

16. The system of claim 15 , wherein the at least one resistor is coupled in series with at least one capacitor of the plurality of capacitors.

17. The system of claim 15 , wherein the at least one resistor is coupled in parallel with at least one capacitor of the plurality of capacitors.

Assignees

• Apple Inc

Inventors

• Ramachandran Vidhya
• Zhong Chonghua
• Searles Shawn
• Zhai Jun
• Jeon Young Doo
• Chen Huabo

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title