Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

Patent metadata

Field	Value
Publication number	US-9548273-B2
Application number	US-201514704714-A
Country	US
Kind code	B2
Filing date	May 5, 2015
Priority date	Dec 4, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Die ( 110 ) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer ( 120 ) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant ( 160 ). Then the interposer is thinned from below. Before encapsulation, a layer ( 410 ) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

First claim

The invention claimed is:

1. A manufacturing method comprising:
obtaining an assembly comprising a first structure and one or more modules, wherein:
the first structure comprises first circuitry comprising one or more first contact pads at a top of the first structure;
the one or more modules are attached to a top surface of the first structure and electrically connected to at least one first contact pad, each module comprising at least one semiconductor integrated circuit;
after obtaining the assembly, forming a first layer on the top surface of the first structure;
forming a second layer overlying the first layer, wherein the second layer has a lower room-temperature elastic modulus than the first layer; and
thinning the first structure from a bottom of the first structure while the first layer is present on said top surface of the first structure;
wherein at least one of the following is true:
(a) the first layer is inorganic;
(b) the first layer is a material different from any material found at an interface between the first structure and at least one of the one or more modules;
(c) during the thinning, the first layer covers all of that portion of said top surface which is not occupied by the one or more modules;
(d) the one or more modules comprise one or more first modules, the assembly comprising underfill between the first structure and each first module, the underfill extending laterally beyond each first module, and during the thinning the first layer covers all of that portion of said top surface which is not occupied by the one or more modules and not covered by the underfill.

2. The method of claim 1 wherein said thinning of the first structure comprises a mechanical thinning process.

3. The method of claim 2 wherein the mechanical thinning process comprises chemical mechanical polishing.

4. The method of claim 2 wherein the first layer reduces or eliminates dishing of the first structure in the mechanical thinning process.

5. The method of claim 1 wherein the first structure is for providing an interposer, and the method provides one or more second contact pads at a bottom of the interposer.

6. The method of claim 5 wherein the one or more second contact pads are part of the first circuitry and become exposed by said thinning.

7. The method of claim 5 further comprising forming additional circuitry in the first structure after the thinning, wherein forming the additional circuitry comprises forming the one or more second contact pads electrically coupled to the first circuitry.

8. The method of claim 5 wherein for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the interposer is closer to the XY CTE of the first layer than to the XY CTE of the second layer.

9. The method of claim 5 wherein for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the first layer is at least 10% of, and at most three times, the XY CTE of the interposer.

10. The method of claim 5 wherein the interposer comprises a substrate supporting the first circuitry; and
for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the substrate is closer to the XY CTE of the first layer than to the XY CTE of the second layer.

11. The method of claim 5 wherein the interposer comprises a substrate supporting the first circuitry; and
for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the first layer is at least 10% of, and at most three times, the XY CTE of the substrate.

12. The method of claim 1 further comprising, before said thinning, attaching a carrier member on top of the second layer, the carrier member having a higher room-temperature elastic modulus than the second layer.

13. The method of claim 12 wherein at least one of the one or more modules is at least partially located in a cavity in the carrier member.

14. The method of claim 1 wherein the first layer is inorganic, and the second layer comprises organic polymeric material.

15. The method of claim 1 wherein (a) is true.

16. The method of claim 1 wherein (b) is true.

17. The method of claim 1 wherein (c) is true.

18. The method of claim 1 wherein (d) is true.

19. The method of claim 1 wherein the first layer physically contacts a sidewall of at least one of the one or more modules at a location where the sidewall has a higher room-temperature elastic modulus than the second layer.

20. The method of claim 1 wherein the second layer physically contacts a sidewall of at least one of the one or more modules.

Assignees

• Invensas Corp

Inventors

• Gao Guilian
• Uzoh Cyprian Emeka
• Woychik Charles G
• Shen Hong
• Sitaram Arkalgud R
• Wang Liang
• Agrawal Akash
• Katkar Rajesh

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title