Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices

Patent metadata

Field	Value
Publication number	US-9546090-B1
Application number	US-201514826449-A
Country	US
Kind code	B1
Filing date	Aug 14, 2015
Priority date	Aug 14, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Integrated MEMS-CMOS devices and methods for fabricating MEMS devices and CMOS devices are provided. An exemplary method for fabricating a MEMS device and a CMOS device includes forming the CMOS device in and/or over a first side of a semiconductor substrate. Further, the method includes forming the MEMS device in and/or under a second side of the semiconductor substrate. The second side of the semiconductor substrate is opposite the first side of the semiconductor substrate.

First claim

What is claimed is:

1. A method for fabricating a MEMS device and a CMOS device, the method comprising:
forming the CMOS device in and/or directly on a first side of a bulk semiconductor wafer; and
etching a via into the first side of the bulk semiconductor wafer;
forming an interconnect in the via;
forming an interlayer dielectric over the CMOS device and the first side of the bulk semiconductor wafer;
etching a first trench through the interlayer dielectric to expose the interconnect;
forming a first conductive structure in the first trench to electrically connect the CMOS device and the interconnect;
recessing a second side of the bulk semiconductor wafer to expose the interconnect;
bonding an intermediate layer and a semiconductor layer to the second side of the bulk semiconductor wafer;
forming the MEMS device directly on the second side of the bulk semiconductor wafer, wherein the second side of the bulk semiconductor wafer is opposite the first side of the bulk semiconductor wafer, wherein forming the MEMS device directly on the second side of the bulk semiconductor wafer comprises forming the MEMS device within the intermediate layer and within the semiconductor layer;
etching a second trench through the semiconductor layer and the intermediate layer to expose the interconnect; and
forming a second conductive structure in the second trench to electrically connect the CMOS device and the interconnect, wherein the second conductive structure contacts the second side of the bulk semiconductor wafer.

2. The method of claim 1 wherein bonding the intermediate layer and the semiconductor layer to the second side of the bulk semiconductor wafer and forming the MEMS device directly on the second side of the bulk semiconductor wafer comprises:
bonding the intermediate layer directly on the second side of the bulk semiconductor wafer;
bonding the semiconductor layer on directly on the intermediate layer; and
etching an opening through the semiconductor layer and through the intermediate layer, wherein the opening is bounded by the second side of the bulk semiconductor wafer.

3. The method of claim 1 wherein forming the CMOS device in and/or directly on the first side of the bulk semiconductor wafer comprises forming the CMOS device in and/or directly on the first side of a high resistivity silicon wafer.

4. The method of claim 1 wherein forming the MEMS device directly on the second side of the bulk semiconductor wafer comprises performing a bulk micromachining process to form the MEMS device in the semiconductor layer.

5. The method of claim 1 further comprising converting the second side of the bulk semiconductor wafer into a trap-rich layer, wherein forming the MEMS device directly on the second side of the bulk semiconductor wafer comprises forming the MEMS device directly on the trap-rich layer.

6. A method for fabricating a vertically integrated MEMS-CMOS device, the method comprising:
providing a semiconductor substrate defining a center plane;
forming a CMOS device on the semiconductor substrate;
forming a MEMS device on the semiconductor substrate, wherein the center plane is located between the CMOS device and the MEMS device; and
electrically connecting the CMOS device and the MEMS device with an interconnect extending through the semiconductor substrate, wherein electrically connecting the CMOS device and the MEMS device with the interconnect extending through the semiconductor substrate comprises:
forming an interlayer dielectric over the CMOS device;
etching a first trench through the interlayer dielectric to expose the interconnect;
forming a first conductive structure in the first trench to electrically connect the CMOS device and the interconnect;
bonding a semiconductor layer to the semiconductor substrate, wherein forming the MEMS device on the semiconductor substrate comprises forming the MEMS device in and/or under the semiconductor layer;
etching a second trench through the semiconductor layer to expose the interconnect; and
forming a second conductive structure in the second trench to electrically connect the CMOS device and the interconnect.

7. The method of claim 6 further comprising:
forming a via through the semiconductor substrate, wherein the via passes through the center plane;
forming the interconnect in the via.

8. The method of claim 6 wherein providing the semiconductor substrate defining a center plane comprises providing a high resistivity silicon wafer.

9. The method of claim 6 further comprising:
forming an interlayer dielectric over the CMOS device, wherein the interlayer dielectric defines an upper surface; and
bonding a protective layer to the upper surface of the interlayer dielectric.

10. The method of claim 6 further comprising:
forming an interlayer dielectric over the CMOS device, wherein the interlayer dielectric defines an upper surface; and
depositing a protective material over the upper surface of the interlayer dielectric.

11. The method of claim 6 wherein forming the MEMS device on the semiconductor substrate comprises performing a bulk micromachining process to form the MEMS device in the semiconductor layer.

12. A method for fabricating a MEMS device and a CMOS device, the method comprising:
forming the CMOS device in and/or over a first side of a semiconductor substrate;
forming an interconnect through the first side of the semiconductor substrate;
forming an interlayer dielectric over the first side of the semiconductor substrate;
etching a first trench through the interlayer dielectric to expose the interconnect;
forming a first conductive structure in the first trench to electrically connect the CMOS device and the interconnect;
bonding a semiconductor layer to a second side of the semiconductor substrate opposite the first side;
forming a MEMS device in and/or under the semiconductor layer;
etching a second trench through the semiconductor layer to expose the interconnect; and
forming a second conductive structure in the second trench to electrically connect the MEMS device and the interconnect.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Xia jia jie
• Ranganathan Nagarajan
• Kumar Rakesh
• Chatterjee Aveek Nath

Classifications

• B81C2203/0735

  Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit · CPC title

• B81B2207/07

  Interconnects · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B81C2201/053

  Depositing a protective layers · CPC title

• B81C2201/013

  Etching · CPC title