P-N bimodal conduction resurf LDMOS

Patent metadata

Field	Value
Publication number	US-9543299-B1
Application number	US-201514861912-A
Country	US
Kind code	B1
Filing date	Sep 22, 2015
Priority date	Sep 22, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

First claim

What is claimed is:

1. A laterally diffused metal oxide semiconductor (LDMOS) device comprising:
an n-type drain;
an n-type source;
a p-type source electrically coupled to the n-type drain;
a p-type drain electrically coupled to the n-type source;
an n-type layer operable to serve as an n-type conduction channel between the n-type drain and the n-type source;
a p-type top layer disposed above and adjacent to said n-type layer, said p-type top layer being operable to serve as a p-type conduction channel between the p-type source and the p-type drain;
an n-gate positioned closer to the n-type source than the n-type drain and operable to control current flow in the n-type conduction channel; and
a p-gate positioned closer to the p-type source than the p-type drain and operable to control current flow in the p-type conduction channel.

2. The LDMOS device of claim 1 , wherein said p-type top layer comprises a p-type RESURF layer.

3. The LDMOS device of claim 1 , wherein:
said n-type drain is coupled to a first n+ implant embedded in said n-type layer;
said n-type source is coupled to a second n+ implant embedded in said n-type layer; and
said p-type source is coupled to a first p+ implant embedded in said n-type layer.

4. The LDMOS device of claim 3 , wherein said p-type drain is coupled to a second p+ implant embedded in said p-type top layer.

5. The LDMOS device of claim 4 , further comprising a second p-type layer buried within said n-type layer and operable to serve as a second p-type conduction channel between the p-type source and the p-type drain.

6. The LDMOS device of claim 5 , wherein said p-type buried layer comprises a p-type RESURF layer.

7. The LDMOS device of claim 5 , wherein said second n+ implant is embedded in an isolated p-type well disposed within the n-type layer, and wherein said p-type drain is coupled to a third p+ implant embedded in said isolated p-type well.

8. The LDMOS device of claim 7 , further comprising a vertical p-type region linking said buried p-type layer and said p-type top layer to enable conduction in said second p-type conduction channel between the p-type source and the p-type drain.

9. The LDMOS device of claim 8 , further comprising a second vertical p-type region linking said buried p-type layer and said isolated p-type well to enable conduction in said second p-type conduction channel between the p-type source and the p-type drain.

10. A laterally diffused metal oxide semiconductor (LDMOS) device comprising:
an n-type metal oxide semiconductor (NMOS) transistor comprising:
an n-type drain;
an n-type source;
an n-type layer operable to serve as an n-type conduction channel between the n-type drain and the n-type source; and
an n-gate positioned closer to the n-type source than the n-type drain and operable to control current flow in the n-type conduction channel; and
a p-type metal oxide semiconductor (PMOS) transistor comprising:
a p-type source electrically coupled to the n-type drain of the NMOS transistor;
a p-type drain electrically coupled to the n-type source of the NMOS transistor;
a p-type top layer disposed above and adjacent to said n-type layer, said p-type top layer being operable to serve as a p-type conduction channel between the p-type source and the p-type drain; and
a p-gate positioned closer to the p-type source than the p-type drain and operable to control current flow in the p-type conduction channel.

11. The LDMOS device of claim 10 , wherein said p-type top layer comprises a p-type RESURF layer.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P
• Edwards Henry Litzmann

Classifications

• H01L29/7817

  Electricity · mapped topic

• H01L27/092 Primary

  Electricity · mapped topic

• H01L29/0878

  Electricity · mapped topic

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D30/657

  having substrates comprising insulating layers, e.g. SOI-LDMOS transistors · CPC title