Power supply glitch detector

Patent metadata

Field	Value
Publication number	US-10156595-B2
Application number	US-201715831287-A
Country	US
Kind code	B2
Filing date	Dec 4, 2017
Priority date	Dec 9, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V bias , wherein V bias is chosen such that either both conditions (V bias <V trip ) and (V bias +V glitch >V trip ) or both conditions (V bias >V trip ) and (V bias −V glitch <V trip ) are always true.

First claim

What is claimed is:

1. A power supply glitch detector comprising:
a sensing node AC coupled to a power supply node on which positive voltage glitches having a magnitude of at least V glitch are to be detected;
a sensing inverter having an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state; and
a user-settable voltage biasing circuit coupled to the sensing node to maintain the input of the sensing inverter at a settable bias voltage V bias , wherein V bias is chosen such that both conditions (V bias <V trip ) and (V bias +V glitch >V trip ) are always true.

2. The power supply glitch detector of claim 1 wherein the sensing node is AC coupled by a capacitor voltage divider to the power supply node on which positive voltage glitches having a magnitude of at least V glitch are to be detected.

3. The power supply glitch detector of claim 1 further comprising a glitch width filter coupled to the output of the sensing inverter.

4. The power supply glitch detector of claim 3 wherein the glitch width filter is a variable pulse width filter.

5. The power supply glitch detector of claim 1 further comprising a pulse stretching circuit coupled to the output of the sensing inverter.

6. The power supply glitch detector of claim 1 wherein the user-settable voltage biasing circuit comprises:
a series string of resistors;
an inverter having a trip voltage V trip equal to the trip voltage of the sensing inverter, the inverter having an input and an output connected together to a first end of the series string of resistors;
an n-channel transistor having a drain coupled to a second end of the series string of resistors, a source coupled to ground, and a gate coupled to a voltage potential selected to cause a predetermined current to flow through the series string of resistors;
a first select transistor coupled between the drain of the n-channel transistor and the sensing node, the first select transistor having a gate coupled to a first control signal; and
a second select transistor coupled between a common connection of a first adjacent pair of resistors in the series string of resistors and the sensing node, the second select transistor having a gate coupled to a second control signal.

7. The power supply glitch detector of claim 6 wherein the user-settable voltage biasing circuit further comprises:
a third select transistor coupled between a common connection of a second adjacent pair of resistors in the series string of resistors and the sensing node, the third select transistor having a gate coupled to a third control signal.

8. A power supply glitch detector comprising:
a sensing node AC coupled to a power supply node on which negative voltage glitches having a magnitude of at least V glitch are to be detected;
a sensing inverter having an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state;
a user-settable voltage biasing circuit coupled to the sensing node to maintain the input of the sensing inverter at a settable bias voltage V bias , wherein V bias is chosen such that both conditions (V bias >V trip ) and (V bias −V glitch <V trip ) are always true.

9. The power supply glitch detector of claim 8 wherein the sensing node is AC coupled by a capacitor voltage divider to the power supply node on which negative voltage glitches having a magnitude of at least V glitch are to be detected.

10. The power supply glitch detector of claim 8 further comprising a glitch width filter coupled to the output of the sensing inverter.

11. The power supply glitch detector of claim 10 wherein the glitch width filter is a variable pulse width filter.

12. The power supply glitch detector of claim 8 further comprising a pulse stretching circuit coupled to the output of the sensing inverter.

13. The power supply glitch detector of claim 8 wherein the user-settable voltage biasing circuit comprises:
a series string of resistors;
a current mirror supplying a current i bias connected to a first end of the series string of resistors;
an inverter having a trip voltage V trip equal to the trip voltage of the sensing inverter, the inverter having an input and an output connected together to a second end of the series string of resistors;
a first select transistor coupled between the output of the current mirror and the sensing node, the first select transistor having a gate coupled to a first control signal; and
a second select transistor coupled between a common connection of a first adjacent pair of resistors in the series string of resistors and the sensing node, the second select transistor having a gate coupled to a second control signal.

14. The power supply glitch detector of claim 13 wherein the user-settable voltage biasing circuit further comprises:
a third select transistor coupled between a common connection of a second adjacent pair of resistors in the series string of resistors and the sensing node, the third select transistor having a gate coupled to a third control signal.

15. A power supply glitch detector comprising:
a first sensing node AC coupled to a power supply node on which positive voltage glitches having a magnitude of at least V glitch+ are to be detected;
a first sensing inverter having an input and an output, the input coupled to the first sensing node, the first sensing inverter having a trip voltage V trip+ below which the output of the first sensing inverter is at a voltage representing a logic high state and above which the output of the first sensing inverter is at a voltage representing a logic low state;
a first user-settable voltage biasing circuit coupled to the first sensing node to maintain the input of the first sensing inverter at a settable bias voltage V bias+ , wherein V bias+ is chosen such that both conditions (V bias+ <V trip+ ) and (V bias+ +V glitch+ >V trip+ ) are always true;
a second sensing node AC coupled to a power supply node on which negative voltage glitches having a magnitude of at least V glitch− are to be detected;
a second sensing inverter having an input and an output, the input coupled to the second sensing node, the second sensing inverter having a trip voltage V trip− below which the output of the second sensing inverter is at a voltage representing a logic high state and above which the output of the second sensing inverter is at a voltage representing a logic low state;
a second user-settable voltage biasing circuit coupled to the second sensing node to maintain the input of the second sensing inverter at a settable bias voltage V bias− , wherein V bias− is chosen such that both conditions (V bia−s >V trip− ) and (V bias− −V glitch− <V trip− ) are always true.

16. The power supply glitch detector of claim 15 wherein:
the first sensing node is AC coupled by a first capacitor voltage divider coupled to the power supply node on which positive voltage glitches having a magnitude of at least V glitch+ are to be detected; and
the second sensing node is AC coupled by a second capacitor voltage divider coupled to the power supply node on which negative voltage glitches having a magnitude of at least V glitch− are to be detected

Assignees

• Microsemi Soc Corp

Inventors

• Nirwan Bhawana Singh
• Lal Abhishek

Classifications

• G01R19/2503

  for measuring voltage only, e.g. digital volt meters (DVM's) (G01R19/2506 - G01R19/257 take precedence) · CPC title

• G01R29/023

  Measuring pulse width · CPC title

• G01R19/165

  Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values · CPC title

• G01R31/317

  Testing of digital circuits · CPC title

• G01R29/02

  Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration · CPC title