Method and algorithm for functional critical paths selection and critical path sensors and controller insertion

Patent metadata

Field	Value
Publication number	US-9536038-B1
Application number	US-201514791446-A
Country	US
Kind code	B1
Filing date	Jul 4, 2015
Priority date	Apr 13, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

CAD software examines delays of paths in a design from design engineers and first selects the longest paths. Then all paths that converge with these longest paths are examined for delays, and a fastest converging path is selected for each of the longest paths. The longest paths are again sorted by the fastest converging delay, and paths with slower converging paths are selected to be Functional Critical Paths (FCP's). Functional critical path timing sensors are added to each FCP to test setup time with an added margin delay. When the margined path delays fail to meet setup requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. The CAD software can replicate some of the FCP's and add toggle pattern generators and timing sensors and a margin controller to adjust the margin delay.

First claim

We claim:

1. An Integrated Circuit (IC) product produced by a process of:
generating path delays for a plurality of paths in an IC design specification;
sorting the path delays and selecting a top M % of paths sorted by maximum path delay;
examining the top M % of paths to locate converging paths;
generating converging path delays for the converging paths;
finding a minimum converging path delay for each of the top M % of paths;
sorting the minimum converging paths delays and selecting a top N % of the top M % of paths having largest minimum converging path delays;
identifying the top N % of the top M % of paths as Functional Critical Paths (FCP);
adding a functional critical path timing sensor to an output of each FCP;
adding a voltage controller that controls a local power-supply voltage to the plurality of paths and to the functional critical path timing sensors;
connecting FCP timing-failure outputs of the functional critical path timing sensors to inputs of the voltage controller,
wherein the voltage controller is for increasing the local power-supply voltage when a FCP timing-failure output is activated, and for decreasing the local power-supply voltage when no FCP timing-failure output has been activated for a period of time;
writing images of the IC product to a plurality of photomasks, the images including images of the functional critical path timing sensors connected to identified FCP's; and
using the plurality of photomasks to print the images onto a semiconductor substrate during steps in an IC manufacturing process to build a plurality of dice of the IC product onto the semiconductor substrate,
whereby the IC product has added circuitry for sensing of timing-failures of selected paths to control the local power-supply voltage to compensate for timing failures.

2. The IC product of claim 1 , wherein generating path delays for the plurality of paths in the IC design specification further comprises:
reading a Register-Transfer-Level (RTL) file that describes behavior of the IC product without control of the local power-supply voltage to compensate for timing failures.

3. The IC product of claim 2 , wherein adding the functional critical path timing sensor and adding the voltage controller further comprise:
adding descriptions of functions performed by the functional critical path timing sensor and by the voltage controller to the RTL file,
whereby sensors and controllers are added as RTL descriptions.

4. The IC product of claim 2 , wherein adding the functional critical path timing sensor and adding the voltage controller further comprise:
adding to a netlist file logic gates and flip-flops that implement the functional critical path timing sensor and the voltage controller,
whereby sensors and controllers are added as gates.

5. The IC product of claim 2 , further comprising:
selecting a subset of the FCP's for replication;
replicating each FCP in the subset of FCP's to create toggling functional critical paths (TFCP's);
adding a constantly-toggling pattern generator and connecting an output of the constantly-toggling pattern generator to inputs of the TFCP's;
adding a toggling functional critical path timing sensor to an output of each TFCP;
adding a margin controller that controls a margin delay value that increases delays in the FCP's and in the TFCP's; and
connecting TFCP timing-failure outputs of the toggling functional critical path timing sensors to inputs of the margin controller,
wherein the margin controller adjusts a margin delay to the toggling functional critical path timing sensors over a range of variable delays to find a minimum variable delay value that causes the TFCP timing-failure outputs to be activated to generate the margin delay value;
whereby the local power-supply voltage is adjusted in response to the FCP timing-failure outputs using variable delays adjusted by the margin controller in response to the TFCP timing-failure outputs.

6. The IC product of claim 5 , wherein M is no more than 1 and N is no more than 10,
wherein the top N % of the top M % of paths selected as Functional Critical Paths are less than 0.1% of all paths in the plurality of paths in the IC design specification.

7. A computer-implemented process to convert a semiconductor chip into a process-compensating semiconductor chip comprising:
performing static timing analysis on a design file that specifies the semiconductor chip to generate a plurality of path delays;
sorting the path delays to obtain a slowest group of paths that are sorted by delay;
identifying converging paths that converge with the slowest group of paths;
identifying a fastest converging path from the converging paths for each path in the slowest group of paths;
discarding paths in the slowest group of paths that have fastest converging paths that are faster than a short-path threshold delay;
identifying paths that are not discarded as Functional Critical Paths (FCP's);
creating an instance of a functional critical path timing sensor for each FCP and connecting and an output of the FCP to the functional critical path timing sensor;
creating an instance of a voltage controller that controls an internal power-supply voltage that powers the slowest group of paths and the functional critical path timing sensors; and
connecting FCP timing failure outputs from the functional critical path timing sensors to inputs of the voltage controller;
wherein the voltage controller is for increasing the internal power-supply voltage when a FCP timing-failure output is activated, and for decreasing the internal power-supply voltage when no FCP timing-failure output has been activated for a period of time,
whereby internal power-supply voltage control in response to FCP timing failures is added to the design file;
generating a critical-path sensing and voltage controlling design file from the design file that specifies the semiconductor chip by adding instances of the functional critical path timing sensors and the voltage controller to the design file;
modifying the critical-path sensing and voltage controlling design file to generate mask image files that control a photomask-making machine that generates a plurality of photomasks;
wherein the plurality of photomasks control printing of images specified in the mask image files onto a semiconductor substrate during a semiconductor manufacturing process to build the semiconductor chip,
wherein the semiconductor chip is built with added functional critical path timing sensors that control the voltage controller to adjust the internal power-supply voltage in response to timing failures detected by the functional critical path timing sensors.

8. The computer-implemented process of claim 7 , further comprising:
selecting a subset of the FCP's for replication;
replicating each FCP in the subset of FCP's to create toggling functional critical paths (TFCP's);
adding a constantly-toggling pattern generator and connecting an output of the constantly-toggling pattern generator to inputs of the TFCP's;
adding a toggling functional critical path timing sensor to an output of each TFCP;
adding a margin controller that controls a margin delay value that increases delays in the FCP's and in the TFCP's; and
connecting TFCP timing-failure outputs of the toggling functional critical path timing sensors to inputs of the margin controller,
wherein the margin controller adjusts a margin delay to the toggling functional critical path timing sensors over a range of variable delays to find a minimum variable delay value that causes the TFCP timing-failure outputs to be activated to generate the margin delay value;
whereby the internal power-supply voltage is adjusted in response to the FCP timing-failure outp

Assignees

• Abreezio LLC
• Qualcomm Inc

Inventors

• Quinton Bradley
• McClements Trent
• Hughes Andrew
• Taneja Sanjiv

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title