Method of isolating bad pixels on a wafer

Patent metadata

Field	Value
Publication number	US-9530820-B1
Application number	US-201615047409-A
Country	US
Kind code	B1
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A method of isolating bad pixels on a wafer comprising the steps of determining physical locations of the bad pixels on the wafer, creating a mask based on the physical locations of the bad pixels, imprinting the mask onto the wafer, and hybridizing the wafer onto a readout integrated circuit (ROIC).

First claim

What is claimed is:

1. A method of isolating bad pixels on a wafer comprising the steps of:
determining physical locations of the bad pixels on the wafer;
creating a mask based on the physical locations of the bad pixels;
imprinting the mask onto the wafer; and
hybridizing the wafer onto a readout integrated circuit (ROIC).

2. The method of claim 1 wherein the wafer comprises a plurality of pixels, each pixel corresponding to a closed via on the mask.

3. The method of claim 2 wherein the step of creating the mask further comprises opening all of the closed vias except for those corresponding to the bad pixels.

4. The method of claim 3 wherein each bad pixel corresponds to a closed via such that the bad pixels are prevented from communicating signals to the ROIC.

5. The method of claim 1 further comprising, after the step of determining physical locations, the steps of:
assigning each of the physical locations of the bad pixels to an X-Y coordinate value; and
plotting the X-Y coordinate values onto an X-Y coordinate plane.

6. The method of claim 5 wherein the mask is created based on the physical locations of the bad pixels as plotted onto the X-Y coordinate plane.

7. The method of claim 1 wherein the wafer comprises a sensor chip assembly (SCA).

8. A method of isolating bad pixels on a wafer comprising the steps of:
establishing alignment targets on the wafer;
determining physical locations of the bad pixels relative to the alignment targets;
translating the physical locations onto a mask; and
imprinting the mask onto the wafer.

9. The method of claim 8 further comprising the step of hybridizing the wafer onto a readout integrated circuit (ROIC) such that the mask prevents electrical coupling between the bad pixels and the ROIC.

10. The method of claim 8 wherein each of the physical locations corresponds to an X-Y coordinate for translation onto the mask.

11. The method of claim 9 wherein the wafer comprises a plurality of pixels, each pixel corresponding to a closed via on the mask.

12. The method of claim 11 wherein the step of imprinting the mask further comprises opening all of the closed vias except for those corresponding to the bad pixels.

13. The method of claim 12 wherein each bad pixel corresponds to a closed via such that the bad pixels are prevented from communicating signals to the ROIC.

14. The method of claim 8 wherein the mask comprises a metal insulating layer.

15. A method of isolating bad pixels on a wafer comprising a plurality of pixels, comprising the steps of:
determining physical locations of good pixels on the wafer;
opening a plurality of closed vias on the wafer corresponding to the physical locations of the good pixels; and
hybridizing the wafer onto a readout integrated circuit (ROIC) comprising a plurality of indium bumps, each of the plurality of indium bumps corresponding to each of the plurality of pixels.

16. The method of claim 15 wherein each bad pixel corresponds to a closed via such that the bad pixels are prevented from communicating signals to the ROIC.

17. The method of claim 15 further comprising, after the step of determining physical locations, the steps of:
assigning each of the physical locations of the good pixels to an X-Y coordinate value; and
plotting the X-Y coordinate values onto an X-Y coordinate plane.

18. The method of claim 17 further comprising creating a mask based on the physical locations of the good pixels as plotted onto the X-Y coordinate plane.

19. The method of claim 18 wherein the mask determines which of the plurality of closed vias is to be opened.

20. The method of claim 15 wherein the wafer comprises a sensor chip assembly (SCA).

Assignees

• Teledyne Scient & Imaging Llc

Inventors

• Douglas Sheri
• Chen Chi Yi
• Ellsworth Jon
• Yulius Aristo
• Meddeler Gerrit

Classifications

• H01L27/14698 Primary

  Electricity · mapped topic

• H01L27/1463

  Electricity · mapped topic

• H01L27/14687

  Electricity · mapped topic

• H01L27/14696

  Electricity · mapped topic

• H10F39/022

  of image sensors having active layers comprising only Group II-VI materials, e.g. CdS, ZnS or CdTe · CPC title