Barrier layer on a piezoelectric-device pad
US-2024314500-A1 · Sep 19, 2024 · US
US9177828B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9177828-B2 |
| Application number | US-201113024806-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 10, 2011 |
| Priority date | Feb 10, 2011 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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Official abstract text for this publication.
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.
Opening claim text (preview).
What is claimed as new and desired to be protected by Letters Patent of the United States is: 1. An external gettering element for providing gettering to a first substrate of a semiconductor device, said first substrate having a front side at which electrical devices are formed and a stress relieved backside opposite the front side, said external gettering element comprising: a first gettering material, wherein said first gettering material contains an additive which provides the…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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