Integrated circuit devices including strained channel regions and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9525053-B2
Application number	US-201414304008-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Nov 1, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness T w sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

First claim

What is claimed:

1. An enhancement-mode field effect transistor, comprising:
a quantum well channel region having a well thickness T w sufficient to yield a strain induced splitting of a plurality of equivalent electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when the surface is biased into a state of inversion.

2. The transistor of claim 1 , wherein the well thickness T w is equivalent to a thickness of the channel region as measured between an insulated gate electrode on the surface and a barrier layer having a bandgap greater than a bandgap of the channel region.

3. The transistor of claim 2 , wherein the barrier layer is lattice matched to the channel region at an interface therebetween.

4. The transistor of claim 2 , wherein the barrier layer comprises zinc sulfide (ZnS).

5. The transistor of claim 1 , wherein the transistor is selected from a group consisting of ultrathin-body silicon-on-insulator (UTB-SOI) transistors and Fin-FETs.

6. The transistor of claim 1 , wherein the channel region comprises a material having degenerate conduction band minima states that are sufficiently spaced from a first Brillouin zone edge to form a plurality of hybridized conduction states due to quantization.

7. The transistor of claim 1 , wherein the channel region comprises silicon or Si x Ge 1-x having a (100) crystal orientation, where x>0.15.

8. The transistor of claim 7 , wherein the well thickness T w is defined by 27 or 34 crystal layers when the channel region comprises silicon having a (100) crystal orientation.

9. The transistor of claim 1 , wherein the channel region comprises GaP having a (100) crystal orientation or carbon with a (100) diamond crystal orientation.

10. A Fin-FET, comprising:
a Fin-shaped semiconductor region comprising a harrier layer spine embedded therein, which is centered equidistant relative to first and second opposing sidewalls of the semiconductor region, said semiconductor region having a width sufficient to yield a strain induced splitting of a plurality of equivalent electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent the first and second opposing sidewalls of the semiconductor region when the first and second sidewalls are biased into a state of inversion.

11. The transistor of claim 10 , wherein:
said semiconductor region comprises first and second quantum well channel regions on opposing sidewalls of the barrier layer; and
the barrier layer has a bandgap greater than bandgaps of the first and second quantum well channel regions.

12. The transistor of claim 11 , wherein the barrier layer is lattice matched to the first and second channel regions at interfaces therebetween.

13. The transistor of claim 11 , wherein the first and second channel regions comprise silicon or Si x Ge 1-x having a (100) crystal orientation, where x>0.15.

14. The transistor of claim 13 , wherein:
a well thickness T w is equivalent to a width of the first channel region as measured between an insulated gate electrode on the first sidewall and the barrier layer; and
the well thickness T w is defined by 27 or 34 crystal layers when the first channel region comprises silicon having a (100) crystal orientation.

15. The transistor of claim 11 , wherein the first and second channel regions comprise GaP having a (100) crystal orientation or carbon with a (100) diamond crystal orientation.

16. The transistor of claim 11 , wherein the first and second channel regions comprise a material having degenerate conduction band minima states that are sufficiently spaced from a first Brillouin zone edge to form a plurality of hybridized conduction states due to quantization.

17. A Fin-FET, comprising:
a Fin-shaped semiconductor region having a width sufficient to yield a strain-induced splitting of a plurality of equivalent electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent first and second opposing sidewalls of the semiconductor region when the first and second sidewalls are biased into a state of inversion.

18. The transistor of claim 17 , wherein:
said Fin-shaped semiconductor region comprises first and second channel regions comprising the first and second opposing sidewalls, respectively; and
the first and second channel regions comprise silicon or Si x Ge 1-x having a (100) crystal orientation, where x>0.15.

19. The transistor of claim 18 , wherein a width of the first channel region is defined by 27 or 34 crystal layers when the first channel region comprises silicon having a (100) crystal orientation.

20. The transistor of claim 17 , wherein:
said Fin-shaped semiconductor region comprises first and second channel regions comprising the first and second opposing sidewalls, respectively; and

the first and second channel regions comprise GaP having a (100) crystal orientation or carbon with a (100) diamond crystal orientation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hatcher Ryan M
• Rodder Mark S
• Bowen Robert C
• Kittl Jorge A

Classifications

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10D62/86

  being Group II-VI materials, e.g. ZnO · CPC title

• H10D62/82

  Heterojunctions · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title