Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9524976-B2
Application number	US-201414341079-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Sep 15, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

First claim

What is claimed is:

1. A method of fabricating a memory device, comprising:
forming a carbon etch stop layer having a first width dimension over a major surface of a substrate;
forming a stack of alternating layers of a first material and a second material different from the first material over the carbon etch stop layer;
etching the stack through a mask to the carbon etch stop layer to form a memory opening having a second width dimension at a bottom of the memory opening proximate to the carbon etch stop layer that is smaller than the first width dimension of the carbon etch stop layer;
removing the carbon etch stop layer while not removing the first material and the second material to provide a void area between the bottom of the memory opening and a top surface of a protrusion comprising a semiconductor material, the void area having a larger width dimension than the second width dimension of the memory opening;
forming at least a portion of a memory film over a sidewall of the memory opening and in the void area while each layer of the first material and each layer of the second material are present within the stack of alternating layers; and
forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening
wherein forming the carbon etch stop layer comprises:
forming a carbon layer over the top surface of the protrusion;
removing portions of the carbon layer to provide the carbon etch stop layer having the first width dimension;
forming a dielectric material layer adjacent to the carbon etch stop layer; and
planarizing the dielectric material layer with a top surface of the carbon etch stop layer, wherein the stack of alternating layers of the first material and the second material is formed over the planarized surface of the carbon etch stop layer and the dielectric material layer.

2. The method of claim 1 , further comprising:
forming a first gate insulating layer over the major surface of the substrate;
forming a conductive select gate electrode over the first gate insulating layer;
etching the conductive select gate electrode layer and the first gate insulating layer through a mask to form an opening having sidewalls and a bottom surface, wherein the sidewalls are at least partially defined by the select gate electrode layer and the first gate insulating layer and the substrate is exposed in the bottom surface of the opening;
forming a second gate insulating layer on the sidewalls and the bottom surface of the opening;
forming a sacrificial carbon spacer layer over the gate insulating layer on the sidewalls of the opening and not over the bottom surface of the opening;
etching the gate insulating layer over the bottom surface of the opening to expose the substrate; and
removing the sacrificial carbon spacer layer to expose the gate insulating layer over the sidewalls of the opening.

3. The method of claim 2 , further comprising:
forming a protrusion comprising a semiconductor material in or over the major surface of a semiconductor substrate, wherein a top surface of the protrusion is substantially parallel to the major surface of the substrate and the carbon etch stop layer is formed over the top surface of the protrusion; and
etching the memory film to expose the top surface of the protrusion;
wherein the semiconductor channel is formed in the memory opening such that the semiconductor channel contacts the top surface of the protrusion.

4. The method of claim 3 , wherein forming the protrusion comprises epitaxially growing a semiconductor material within the opening between the two select gate electrodes.

5. The method of claim 4 , further comprising:
planarizing the epitaxially grown semiconductor material to form the top surface of the protrusion.

6. The method of claim 5 , wherein the semiconductor material is planarized by at least one of chemical-mechanical polishing and an etch back process.

7. The method of claim 4 , wherein the epitaxially grown semiconductor material comprises silicon.

8. The method of claim 4 , further comprising:
forming a doped region in a top surface of the protrusion.

9. The method of claim 3 , further comprising:
forming a sacrificial material layer over the memory film along at least the sidewall of the memory opening; and
etching the memory film at the bottom of the memory hole to expose the top surface of the protrusion while the sacrificial material layer protects the memory film along the sidewall of the memory opening.

10. The method of claim 9 , wherein the sacrificial material layer comprises a semiconductor material that is formed over the memory film along the sidewall and bottom of the memory opening, and a portion of the sacrificial semiconductor material layer is etched with the memory film to expose the top surface of the protrusion.

11. The method of claim 10 , wherein the sacrificial material layer comprises polysilicon.

12. The method of claim 10 , wherein at least a portion of the sacrificial semiconductor material layer remains in the memory opening when the semiconductor channel is formed in the memory opening.

13. The method of claim 9 , wherein the sacrificial material layer comprises at least one of silicon nitride and carbon.

14. The method of claim 13 , further comprising removing substantially all of the sacrificial material layer from the memory opening before forming the semiconductor channel in the memory opening.

15. The method of claim 13 , wherein the sacrificial material layer comprises carbon.

16. The method of claim 15 , wherein the carbon is deposited so that it preferentially forms on the sidewall of the memory opening and not on the bottom surface of the memory opening.

17. The method of claim 15 , wherein the carbon sacrificial layer protects the at least a portion of the memory film along the sidewall of the memory opening while the memory film is etched in the bottom of the memory opening to expose the top surface of the protrusion.

18. The method of claim 15 , wherein the carbon sacrificial layer is removed from the memory opening by ashing.

19. The method of claim 1 , wherein removing the carbon etch stop layer comprises ashing the carbon etch stop layer.

20. The method of claim 1 , wherein forming the semiconductor channel in the memory opening comprises:
depositing amorphous silicon in the memory opening; and
converting at least a portion of the amorphous silicon to single crystal silicon or polysilicon using a recrystallization process.

21. The method of claim 1 , further comprising:
depositing a dielectric material in a core of the memory opening such that the semiconductor channel concentrically surrounds the dielectric material.

22. The method of claim 21 , wherein the dielectric material comprises SiO 2 .

23. The method of claim 1 , wherein the protrusion contacts a second portion of the semiconductor channel in or above the substrate that extends substantially parallel to the major surface of the substrate.

24. The method of claim 1 , wherein the least one memory film comprises a charge trapping layer or floating gate and a tunnel dielectric, and the tunnel dielectric is located between the charge trapping layer or floating gate and the semiconductor channel.

25. The method of claim 24 , wherein the at least one memory film further comprises a blocking dielectric.

26.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pachamuthu Jayavel
• Alsmeier Johann
• Chien Henry

Classifications

• H01L27/11578

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic