Semiconductor structures and fabrication methods thereof

Patent metadata

Field	Value
Publication number	US-9524933-B2
Application number	US-201514848802-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Oct 28, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a dielectric layer covering a surface of the substrate;
forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer using a first patterned mask layer;
forming first conductive vias by filling the plurality of first through holes using a first metal material and forming first conductive lines over the first conductive vias also using the first metal material;
forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer using a second patterned mask layer; and
forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and forming second conductive lines over the second conductive vias also using the second metal material, wherein:
the anti-electromigration ability of the second metal material is greater than the anti-electromigration ability of the first metal material;
the first conductive vias and the first conductive lines are configured as signal lines of the semiconductor structure; and
the second conductive vias and the second conductive lines are configured as power lines of the semiconductor structure.

2. The method according to claim 1 , wherein:
the first metal material is one of aluminum and tungsten; and
the second metal material is copper.

3. The method according to claim 2 , wherein:
the second conductive vias and the second conductive lines are formed by a flowable physical vapor deposition process; and
the flowable physical vapor deposition process includes an amber physical vapor deposition process.

4. The method according to claim 3 , wherein forming the second conducive vias and the second conductive lines further:
forming a copper film on the dielectric layer; and
performing the amber vapor deposition process to cause copper atoms to reach bottoms of the second through holes under an capillary action until the second through holes are filled.

5. The method according to claim 2 , wherein forming the first conducive vias and the first conductive lines further includes:
forming a first conductive film on the first dielectric layer after forming the plurality of the first through holes;
patterning the first conductive film to form the first conductive vias in the dielectric layer and the first conductive lines on the first conductive vias covering a portion of the surface of the dielectric layer.

6. The method according to claim 5 , after forming the first conductive vias and the first conductive lines and before forming the second conductive vias and the second conductive lines, further including:
forming an insulation layer covering the surface of the dielectric layer and side surfaces of the first conductive lines.

7. The method according to claim 6 , wherein forming the second conductive vias and the second conductive lines further includes:
etching the insulation layer and the dielectric layer to form a plurality of second trenches in the insulation layer and second through holes with a width smaller than a width of the second trenches on bottoms of the second trenches in the dielectric layer to expose the surface of the substrate; and
forming second conductive vias in the second through holes and second conductive lines on the second conductive vias in the second trenches with a top surface leveling with top surfaces of the first conductive lines.

8. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a dielectric layer covering a surface of the substrate;
forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer using a first patterned mask layer;
forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines over the first conductive vias also using the first metal material;
forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer using a second patterned mask layer; and
forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein:
the second metal material has a different anti-electromigration ability from the first metal material;
the second conductive vias are formed after forming the first conductive via and before forming the first conductive lines; and
the first conductive lines are formed after forming the second conductive vias and before forming the second conductive lines.

9. The method according to claim 8 , wherein forming the first conductive lines further includes:
forming a first initial line film on a surface of the dielectric layer and top surfaces of the first conductive vias; and
etching a portion of the first initial line film on the dielectric layer to form the first conductive lines on the first conductive vias and a portion of the dielectric layer.

10. The method according to claim 9 , wherein forming the second conductive lines further includes:
forming an insulation layer covering the surface of the dielectric layer, surfaces of the second conductive vias and side surfaces of the first conducive lines;
etching the insulation layer to expose the top surfaces of the second conductive vias to form second trenches exposing the second conductive vias in the insulation layer; and
forming second conductive lines on the second conductive vias in the second trenches.

11. The method according to claim 8 , wherein forming the second conductive lines further includes:
forming an insulation layer on the surface of the dielectric layer, top surfaces of the plurality of first conductive vias; and top surfaces of the plurality of second conductive vias;
etching the insulation layer to expose the top surfaces of the first conductive vias;
forming first conductive lines on the first conductive vias in the first trenches;
etching the insulation layer to expose the top surfaces of the second conductive vias; and
forming second conductive lines on the first conductive vias in the second trenches.

12. The method according to claim 2 , before forming the first conductive conductive vias, the first conductive lines, the second conductive vias and the second conductive lines, further including:
forming an insulation layer on the dielectric layer.

13. The method according to claim 12 , wherein forming the first through holes, the first conductive vias, and the first conductive lines further includes:
etching the insulation layer and the dielectric layer to form a plurality of first trenches in the insulation layer and a plurality of first through holes with a width smaller than a width of the first trenches on bottoms of the first trenches in the dielectric layer to expose the surface of the substrate; and
forming first conducive vias in the first through holes and first conducive lines on the first conductive vias in the first trenches.

14. The method according to claim 13 , wherein forming the second through holes, the second conductive vias, and second conductive lines further includes:
etching the insulation layer and the dielectric layer to form a plurality of second trenches in the insulation layer and second through holes with a width smaller than a width of the second trenches on bottoms of the second trenches to exp

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zhang Haiyang
• Zhang Chenglong

Classifications

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421 Primary

  the principal metal being copper · CPC title