Flexible APS X-ray imager with MOTFT pixel readout and a pin diode sensing element

US9520437B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9520437-B2
Application numberUS-201414460054-A
CountryUS
Kind codeB2
Filing dateAug 14, 2014
Priority dateAug 14, 2014
Publication dateDec 13, 2016
Grant dateDec 13, 2016

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Abstract

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A method of fabricating an X-ray imager including the steps of forming an etch stop layer on a glass substrate and depositing a stack of semiconductor layers on the etch stop layer to form a sensor plane. Separating the stack into an array of PIN photodiodes. Depositing a layer of insulating material on the array to form a planarized surface and forming vias through the insulating layer into communication with an upper surface of each photodiode and forming metal contacts on the planarized surface through the vias in contact with each photodiode. Fabricating an array of MOTFTs in an active pixel sensor configuration backplane on the planarized surface and in electrical communication with the contacts, to provide a sensor plane/MOTFT backplane interconnected combination. Attaching a flexible support carrier to the MOTFT backplane and removing the glass substrate. A scintillator is then laminated on the array of photodiodes.

First claim

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Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is: 1. A method of fabricating an X-ray imager comprising the steps of: providing a rigid support member with a surface; forming an etch stop layer on the surface of the rigid support member; depositing sensing element blanket layers on the etch stop layer; separating the sensing element blanket layers into an array of sensing elements; depositing a layer of insulating material on the array of sensing elements to form a planarized surface; forming contacts on the planarized surface with individual sensing elements in the array through the layer of insulating material; positioning a MOTFT backplane on the planarized surface and in electrical communication with the contacts, to provide a sensor plane/MOTFT backplane interconnected combination; attaching a support carrier to the MOTFT backplane; removing the rigid support member; and laminating a scintillator on the array of sensing elements. 2. A method as claimed in claim 1 wherein the step of depositing sensing element blanket layers on the etch stop layer includes depositing multiple semiconductor layers, forming a PIN photodiode plane. 3. A method as claimed in claim 2 wherein the step of forming the PIN photodiode plane includes process temperatures higher than process temperatures included in the step of positioning the MOTFT backplane. 4. A method as claimed in claim 2 wherein the step of depositing sensing element blanket layers, the multiple semiconductor layers include at least one of amorphous silicon, amorphous germanium, and amorphous selenium. 5. A method as claimed in claim 2 wherein the step of depositing sensing element blanket layers, the multiple semiconductor layers comprise compound semiconductor materials including at least one of Zn—O, In—Zn—O, Ti—O, Ta—O, W—O, Zr—O, Cd—S, Cd—O, Cu—O, Cu—S, Cu—In—O, Cu—In—Se, Cu—In—S, Cu—Cd—O, Cu—Cd—Se, Cu—Cd—S, Cu—Ga—S, Cu—Ga—O, Cu—Ga—Se, Cu—In—Ga—Se, Cu—In—Ga—S, Mo—O, Ag x MoO 3-x , and combinations in blend or in stack form. 6. A method as claimed in claim 1 wherein the step of depositing sensing element blanket layers on the etch stop layer includes depositing a first p or n doped layer, an intrinsic layer, and a second n or p doped layer, forming a PIN photodiode plane. 7. A method as claimed in claim 6 wherein the step of separating the sensing element blanket layers into an array of sensing elements includes patterning the second n or p doped layer to define individual PIN photodiodes. 8. A method as claimed in claim 7 wherein the step of separating the sensing element blanket layers into an array of sensing elements includes further patterning the intrinsic layer to define individual PIN photodiodes. 9. A method as claimed in claim 1 wherein the step of depositing a layer of insulating material includes depositing material including one of organic or inorganic insulating material including SU-8, polyimide, JSR PCS548, AZ SOG series, silane or siloxane based photo-patternable polymers, SiN, SiON, SiO x , or combinations thereof in blend form or in stack multiple sublayers. 10. A method as claimed in claim 9 wherein the step of depositing the layer of insulating material including one of organic or inorganic insulating material includes depositing an inorganic sublayer in contact with the PIN sensing elements and a photo-patternable organic insulator layer in contact with the MOTFT backplane. 11. A method as claimed in claim 1 wherein the step of forming the etch stop layer includes forming a layer including one of a noble metal and poly-Si. 12. A method as claimed in claim 11 wherein the step of forming the etch stop layer including one of a noble metal and poly-Si includes forming the etch stop layer with a thickness of less than 200 nm. 13. A method as claimed in claim 1 wherein the step of forming contacts on the planarized surface includes forming vias through the layer of insulating material and introducing metal contacts through the vias. 14. A method as claimed in claim 1 wherein the step of positioning the MOTFT backplane on the planarized surface includes fabricating an array of MOTFTs in an active pixel sensor configuration. 15. A method as claimed in claim 14 wherein the step of fabricating the array of MOTFTs in the active pixel sensor configuration includes forming each active pixel sensor with signal amplification. 16. A method as claimed in claim 1 wherein the step of attaching the support carrier includes attaching a flexible support carrier. 17. A method as claimed in claim 1 wherein the step of providing the rigid support member includes providing a glass substrate. 18. A method as claimed in claim 17 wherein the step of removing the rigid support member includes etching the glass substrate using HF. 19. A method as claimed in claim 1 further including a step of removing the etch stop layer subsequent to the step of removing the rigid support member. 20. A method of fabricating an X-ray imager comprising the steps of: providing a glass substrate with a surface; forming an etch stop layer including one of a noble metal and poly-Si on the surface of the glass substrate; depositing a stack of elemental or compound semiconductor layers on the etch stop layer, the stack including a first p or n doped layer, an intrinsic layer, and a second n or p doped layer, forming a PIN photodiode plane; separating the stack of semiconductor layers into an array of PIN photodiodes; depositing a layer of insulating material on the array of sensing elements to form a planarized surface and forming vias through the planarizing layer into communication with an upper surface of each PIN photodiode in the array of PIN photodiodes; forming metal contacts on the planarized surface and through the vias in contact with the upper surface of each PIN photodiode in the array of PIN photodiodes; fabricating an array of MOTFTs in an active pixel sensor configuration backplane on the planarized surface and in electrical communication with the contacts, to provide a sensor plane/MOTFT backplane interconnected combination; attaching a flexible support carrier to the MOTFT backplane; removing the glass substrate; and laminating a scintillator on the array of PIN photodiodes.

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What does patent US9520437B2 cover?
A method of fabricating an X-ray imager including the steps of forming an etch stop layer on a glass substrate and depositing a stack of semiconductor layers on the etch stop layer to form a sensor plane. Separating the stack into an array of PIN photodiodes. Depositing a layer of insulating material on the array to form a planarized surface and forming vias through the insulating layer into co…
Who is the assignee on this patent?
Shieh Chan-Long, Yu Gang, Cbrite Inc
What technology area does this patent fall under?
Primary CPC classification H01L27/14663. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).