Thermal matched composite die

Patent metadata

Field	Value
Publication number	US-9520378-B2
Application number	US-201213725356-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Dec 21, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.

First claim

What is claimed is:

1. An apparatus comprising:
a metal plate;
a semiconductor die configured to carry microelectronic circuits and connectors formed on a back end of substrate, the substrate having a linear coefficient of thermal expansion (CTE) lower than the metal plate; and
an adhesive layer on the front end of the substrate opposite the back end between the substrate and the metal plate to physically attach and mechanically couple the metal plate to the substrate so that the combined metal plate and substrate form a composite that has a higher CTE than the substrate alone, the adhesive layer having a first sub-layer proximate the substrate and a second sub-layer proximate the metal, the first and second sub-layers being gradated structures.

2. The apparatus of claim 1 , wherein the substrate is formed of at least one of silicon, glass, germanium, III-IV, silicon-on-insulator, and ceramic.

3. The apparatus of claim 1 , where in the substrate is configured to carry solder and wherein the adhesive layer is bonded to metal and the substrate at a temperature lower than the melting temperature of the solder.

4. The apparatus of claim 1 , wherein the first sub-layer of the adhesive layer includes a silicon preferential portion to bond to the substrate and the second sub-layer of the adhesive layer has a metal preferential portion to bond to the metal, the two portions being bonded to each other.

5. The apparatus of claim 4 , wherein the silicon preferential portion is applied to the substrate and the metal preferential portion is applied to the metal plate and where in the two portions are pressed together to bond the silicon substrate to the metal plate.

6. The apparatus of claim 5 , wherein the first sub-layer comprises epoxy.

7. The apparatus of claim 6 , wherein the first sub-layer comprises a zirconium alkoxide with epoxy functionalized silane to form a sol-gel network.

8. The apparatus of claim 1 , wherein the metal plate has a thickness that is twice the thickness of the semiconductor die.

9. The apparatus of claim 1 , wherein the adhesive layer comprises terpene phenols proximate the metal plate, zirconia proximate the silicon substrate, and epoxy between the terpene phenols and the zirconia.

10. The apparatus of claim 4 , wherein the adhesive layer comprises gradations of terpene phenols proximate and adhered to the metal plate, amines proximate and adhered to the terpene phenols, epoxy proximate and adhered to the amines, and zirconia proximate and adhered to the silicon substrate.

11. The apparatus of claim 1 , wherein the metal plate comprises copper, the apparatus further comprising a copper diffusion barrier between the metal plate and the adhesive layer.

12. An apparatus comprising:
a communications chip;
a mass memory; and
a processor formed on a packaged die, the packaged die having a metal plate, a semiconductor die configured to carry microelectronic circuits and connectors formed on a back end of a substrate having a linear coefficient of thermal expansion (CTE) lower than the metal plate, and an adhesive layer on the front end of the substrate opposite the back end between the substrate and the metal plate to physically attach and mechanically couple the metal plate to the substrate so that the combined metal plate and substrate form a composite that has a higher CTE than the substrate alone, the adhesive layer having a first sub-layer proximate the substrate with a higher amount of zirconia than a second sub-layer proximate the metal that has more epoxy than the first sub-layer, the first and second sub-layers being gradated structures.

13. The method of claim 12 , wherein applying the first adhesive layer comprises depositing a metal preferential adhesive layer on the metal plate.

14. The method of claim 12 , wherein applying the second adhesive layer comprises spin coating a silicon preferential adhesive on the substrate.

15. The method of claim 12 , wherein pressing comprises pressure bonding.

16. The method of claim 12 , further comprising applying a metal diffusion barrier to the metal plate before applying the first adhesive layer.

17. The method of claim 12 , further comprising surface treating the metal plate before applying the second adhesive layer.

18. An apparatus comprising:
a communications chip;
a mass memory; and
a processor formed on a packaged die, the packaged die having a metal plate, a semiconductor die comprising microelectronic circuits and connectors formed on a back end of a substrate, the substrate having a linear coefficient of thermal expansion (CTE) lower than the metal plate, and an adhesive layer on the front end of the substrate opposite the back end between the substrate and the metal plate to physically attach and mechanically couple the metal plate to the substrate so that the combined metal plate and substrate form a composite that has a higher CTE than the substrate alone, the adhesive layer having a first sub-layer proximate the substrate with a higher layer of zirconia than a second sub-layer proximate the metal that has more epoxy than the first sub-layer, the first and second sub-layers being gradated structures.

19. The apparatus of claim 18 , the packaged die further comprising a cooler directly attached to the metal plate.

20. The apparatus of claim 18 , wherein substrate comprises silicon with semiconductors and metal layers formed thereon.

Assignees

• Aleksov Aleksandar
• Liff Shawna M
• Intel Corp

Inventors

• Aleksov Aleksandar
• Liff Shawna M

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/07338

  hardening the adhesive by curing, e.g. thermosetting · CPC title

• H10W72/07331

  Connecting techniques · CPC title