Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
US-9520350-B2 · Dec 13, 2016 · US
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Raorane Digvijay A patents
Raorane Digvijay A holds 4 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 4 |
| Recent patents | 0 |
| First publication | Feb 17, 2015 |
| Latest publication | Dec 13, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Method to increase I/O density and reduce layer counts in BBUL packages
US-9041207-B2 · May 26, 2015 · US
Multichip integration with through silicon via (TSV) die embedded in package
US-9000599-B2 · Apr 7, 2015 · US
Receptors useful for gas phase chemical sensing
US-8957013-B2 · Feb 17, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
US-9520350-B2 · Dec 13, 2016 · US
Method to increase I/O density and reduce layer counts in BBUL packages
US-9041207-B2 · May 26, 2015 · US
Multichip integration with through silicon via (TSV) die embedded in package
US-9000599-B2 · Apr 7, 2015 · US
Receptors useful for gas phase chemical sensing
US-8957013-B2 · Feb 17, 2015 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10W74/142 | 3 |
| H10W72/241 | 3 |
| H10W70/09 | 3 |
| H10W70/685 | 3 |
| H10W70/60 | 2 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 3 |
| Chemistry & Metallurgy | 1 |
| Physics | 1 |