Method and apparatus for power throttling of highspeed multi-lane serial links

US9519331B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9519331-B2
Application numberUS-201314051612-A
CountryUS
Kind codeB2
Filing dateOct 11, 2013
Priority dateOct 22, 2007
Publication dateDec 13, 2016
Grant dateDec 13, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for managing the power consumption of an information handling system comprising: determining at regularly defined intervals a number of lanes required for a multi-lane serial link, wherein the multi-lane serial link is connected to a host associated with the information handling system, wherein the regularly defined intervals are based on initialization of the host, and wherein the number of lanes required is based on: determining a number of one or more powered-on I/O devices connected to the multi-lane serial link, determining a number of one or more powered-off I/O devices connected to the multi-lane serial link, including in the number of lanes required lanes for the number of one or more powered-on I/O devices, and excluding from the number of lanes required lanes for the number of one or more powered-off I/O devices; triggering a reduction of a lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, the lane setting based on the number of active lanes in the multi-lane serial link; triggering a reduction of the lane setting of the multi-lane serial link if a powered-on I/O device is powered-off; and automatically increasing the lane setting of the multi-lane serial link if an additional powered-on I/O device is connected to the information handling system through the multi-lane serial link. 2. The method of claim 1 , further comprising reducing power to the multi-lane serial link in response to the reduction of the lane setting. 3. The method of claim 2 , wherein reducing power to the multi-lane serial link includes eliminating power to unused lanes of the multi-lane serial link. 4. The method of claim 2 , further comprising: triggering an increase of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is less than the determined number of lanes required; and increasing power to the multi-lane serial link in response to the increase of the lane setting. 5. The method of claim 1 , further comprising decreasing the lane setting of the multi-lane serial link if a powered-on I/O device is removed from the information handling system through the multi-lane serial link. 6. The method of claim 1 , wherein determining the number of lanes required for the multi-lane serial link is performed by a boot monitor and wherein triggering of the reduction of the lane setting of the multi-link serial link is performed by the boot monitor. 7. The method of claim 1 , wherein determining the number of lanes required for the multi-lane serial link includes determining the type of the one or more powered-on I/O devices connected to the multi-lane serial link. 8. An information handling system comprising: a host; a multi-lane serial link connecting one or more I/O devices to the host; the multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link; and a baseboard management controller associated with the host configured to: determine at regularly defined intervals a number of lanes required for the multi-lane serial link, wherein the number of lanes required is based on: determining a number of one or more powered-on I/O devices connected to the multi-lane serial link, determining a number of one or more powered-off I/O devices connected to the multi-lane serial link, including in the number of lanes required lanes for the number of one or more powered-on I/O devices, and excluding from the number of lanes required lanes for the number of one or more powered-off I/O devices; trigger a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, the regularly defined intervals based on initialization of the host; trigger a reduction of the lane setting of the multi-lane serial link if a powered-on I/O device is powered-off; and automatically increase the lane setting of the multi-lane serial link if an additional powered-on I/O device is connected to the host through the multi-lane serial link. 9. The information handling system of claim 8 , wherein the baseboard management controller reduces power to the multi-lane serial link in response to the reduction of the lane setting. 10. The information handling system of claim 9 , wherein reducing power to the multi-lane serial link includes eliminating power to unused lanes of the multi-lane serial link. 11. The information handling system of claim 9 , wherein the baseboard management controller triggers an increase of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is less than the determined number of lanes required and increases power to the multi-lane serial link in response to the increase of the lane setting. 12. The information handling system of claim 8 , wherein the baseboard management controller decreases the lane setting of the multi-lane serial link if the number of the one or more powered-on I/O devices connected to the host through the multi-lane serial link is decreased. 13. The information handling system of claim 8 , wherein the baseboard management controller determines a bandwidth requirement of the one or more powered-on I/O devices connected to the host through the multi-lane serial link based on the number of the one or more powered-on I/O devices. 14. The information handling system of claim 8 , wherein the baseboard management controller determines a bandwidth requirement of the one or more powered-on I/O devices connected to the host through the multi-lane serial link based on the type of the one or more powered-on I/O devices. 15. A computer program product comprising computer executable instructions, stored on a non-transitory tangible computer readable medium, for managing the power consumption of a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link, the instructions comprising: instructions for determining at regularly defined intervals a number of lanes required for the multi-lane serial link, wherein the regularly defined intervals are based on initialization of the host, and wherein the number of lanes required is based on: determining a number of one or more powered-on I/O devices connected to the multi-lane serial link, determining a number of one or more powered-off I/O devices connected to the multi-lane serial link, including in the number of lanes required lanes for the number of one or more powered-on I/O devices, and excluding from the number of lanes required lanes for the number of one or more powered-off I/O devices; instructions for triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required; instructions for triggering a reduction of the lane setting of the multi-lane serial link if a powered-on I/O device is powered-off; and instructions for automatically increasing the lane setting of the multi-lane serial link if an additional I/O device is connected to the host through the multi-lane serial link. 16. The computer program product of claim 15 , further comprising instructions for reducing power to the multi-lane serial link in response to the reduction of the lane setting. 17. The computer program product of claim 16 , wherein reducing power to the multi-lane serial link includes eliminating power to unused

Assignees

Inventors

Classifications

  • Monitoring of peripheral devices · CPC title

  • Cross-Sectional Technologies · mapped topic

  • G06F1/3253Primary

    Power saving in bus · CPC title

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9519331B2 cover?
A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a red…
Who is the assignee on this patent?
Khatri Mukund, Zaretsky Lee, Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification G06F1/3253. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).