Silicon carbide semiconductor device having layer covering corner portion of depressed portion

Patent metadata

Field	Value
Publication number	US-9515197-B2
Application number	US-201214235116-A
Country	US
Kind code	B2
Filing date	Aug 10, 2012
Priority date	Aug 24, 2011
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

In a silicon carbide semiconductor device, a trench penetrates a source region and a first gate region and reaches a drift layer. On an inner wall of the trench, a channel layer of a first conductivity-type is formed by epitaxial growth. On the channel layer, a second gate region of a second conductivity-type is formed. A first depressed portion is formed at an end portion of the trench to a position deeper than a thickness of the source region so as to remove the source region at the end portion of the trench. A corner portion of the first depressed portion is covered by a second conductivity-type layer.

First claim

The invention claimed is:

1. A silicon carbide semiconductor device comprising a JFET, the JFET including:
a semiconductor substrate including a first conductivity-type substrate made of silicon carbide, a drift layer of a first conductivity-type formed on the first conductivity-type substrate by epitaxial growth, a first gate region of a second conductivity-type formed on the drift layer by epitaxial growth, and a source region of the first conductivity-type formed on the first gate region by epitaxial growth or ion implantation;
a trench penetrating the source region and the first gate region and reaching the drift layer, the trench having a strip shape including a longitudinal direction set in one direction;
a channel layer of the first conductivity-type formed on an inner wall of the trench by epitaxial growth;
a second gate region of the second conductivity-type formed on the channel layer;
a first depressed portion formed at an end portion of the trench, the first depressed portion extending to a position deeper than a thickness of the source region by removal of the source region from the end portion of the trench;
a second conductivity-type layer covering only a corner portion at a boundary between a bottom surface and a side surface of the first depressed portion; and
the corner portion of the first depressed portion being filled with the second conductivity-type layer and having a rounded shape,
wherein a second conductivity-type impurity concentration of the second conductivity-type layer is equal to or higher than 1×10 18 cm −3 .

2. The silicon carbide semiconductor according to claim 1 , wherein
a second depressed portion formed at a peripheral region surrounding the source region, the second depressed portion being deeper than the source region and reaching the drift layer;
a RESURF layer of the second conductivity-type formed in the drift layer so as to extend from a side surface to a bottom surface of the second depressed portion; and
a second conductivity-type layer covering a corner portion at a boundary between the bottom surface and the side surface of the second depressed portion.

3. The silicon carbide semiconductor device according to claim 1 ,
wherein the rounded shape of the corner portion of the first depressed portion filled with the second conductivity-type layer is a rounded cross-sectional shape.

4. The silicon carbide semiconductor device according to claim 1 ,
wherein the second conductivity-type layer has a surface extending along a length of the corner of the boundary of the first depressed portion and at an angle from each of the bottom surface and side surface of the first depressed portion is a rounded cross-sectional shape.

5. A silicon carbide semiconductor device comprising a JFET, the JFET including:
a semiconductor substrate including a first conductivity-type substrate made of silicon carbide, a drift layer of a first conductivity-type formed on the first conductivity-type substrate by epitaxial growth, a first gate region of a second conductivity type formed on the drift layer by epitaxial growth, and a source region of the first conductivity-type formed on the first gate region by epitaxial growth or ion implantation;
a trench penetrating the source region and the first gate region and reaching the drift layer, the trench having a strip shape including a longitudinal direction set in one direction;
a channel layer of the first conductivity-type formed on an inner wall of the trench by epitaxial growth;
a second gate region of the second conductivity-type formed on the channel layer;
a first depressed portion formed at an end portion of the trench, the first depressed portion extending to a position deeper than a thickness of the source region by removal of the source region from the end portion of the trench;
a second conductivity-type layer covering only a corner portion at a boundary between a bottom surface and a side surface of the first depressed portion;
a cell region in which a cell of the JFET is formed; and
a peripheral region surrounding the cell region,
wherein the peripheral region includes a second depressed portion deeper than the first gate region and reaching the drift layer, a RESURF layer of the second conductivity-type formed in the drift layer so as to extend from a side surface to a bottom surface of the second depressed portion, and a second conductivity-type layer covering a corner portion at a boundary between the bottom surface and the side surface of the second depressed portion.

Assignees

• Takeuchi Yuichi
• Denso Corp

Inventors

• Takeuchi Yuichi

Classifications

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P32/172

  being crystalline silicon carbide · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title

• H10D62/328

  having PN junction gates · CPC title

• H10D84/035

  using silicon carbide [SiC] technology · CPC title