Semiconductor arrangement with multiple-height fins and substrate trenches

Patent metadata

Field	Value
Publication number	US-9515184-B2
Application number	US-201314024885-A
Country	US
Kind code	B2
Filing date	Sep 12, 2013
Priority date	Sep 12, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
a semiconductor substrate;
a planar region disposed over the semiconductor substrate, the planar region comprising a planar structure; and
a semiconductor fin region disposed over the semiconductor substrate, the semiconductor fin region comprising:
a first fin nub protruding from the semiconductor substrate and formed between a first set of semiconductor fins and a second set of semiconductor fins, wherein:
the first fin nub protrudes from a top surface of the semiconductor substrate, and
a first nub height of the first fin nub, measured from a top surface of the first fin nub to the top surface of the semiconductor substrate from which the first fin nub protrudes, is less than a first fin height of a first fin within the first set of semiconductor fins; and

a first trench formed into the semiconductor substrate, wherein:
the first trench extends below the top surface of the semiconductor substrate from which the first fin nub protrudes, and
the first trench is formed between the first set of semiconductor fins and the second set of semiconductor fins.

2. The semiconductor arrangement of claim 1 , the semiconductor fin region comprising:
a second trench formed into the semiconductor substrate, the second trench formed between the first set of semiconductor fins and the second set of semiconductor fins.

3. The semiconductor arrangement of claim 2 , the first fin nub formed between the first trench and the second trench.

4. The semiconductor arrangement of claim 3 , the semiconductor fin region comprising:
a second fin nub formed between the first trench and the second trench.

5. The semiconductor arrangement of claim 1 , the planar structure comprising:
an alignment mark.

6. The semiconductor arrangement of claim 1 , the semiconductor fin region comprising:
a second fin nub formed between the first set of semiconductor fins and the second set of semiconductor fins.

7. The semiconductor arrangement of claim 1 , the semiconductor fin region comprising:
a first pillar formed between the first set of semiconductor fins and the first trench.

8. The semiconductor arrangement of claim 7 , the first pillar having a first pillar height that is greater than the first nub height.

9. The semiconductor arrangement of claim 7 , the first pillar having a first pillar height that is less than the first fin height of the first fin.

10. The semiconductor arrangement of claim 1 , a first trench depth of the first trench less than the first fin height of the first fin.

11. The semiconductor arrangement of claim 1 , the semiconductor fin region comprising:
a shallow trench isolation (STI) layer formed over the first fin nub.

12. A semiconductor arrangement, comprising:
a semiconductor substrate; and
a semiconductor fin region disposed over the semiconductor substrate, the semiconductor fin region comprising:
a first fin nub protruding from the semiconductor substrate and formed between a first set of semiconductor fins and a second set of semiconductor fins;
a first pillar protruding from the semiconductor substrate and formed between the first set of semiconductor fins and the first fin nub, the first pillar having a first pillar height that is greater than a first nub height of the first fin nub; and
a first trench formed into the semiconductor substrate and between the first fin nub and the first pillar, wherein:
the first fin nub protrudes from a top surface of the semiconductor substrate; and
the first trench extends below the top surface of the semiconductor substrate from which the first fin nub protrudes.

13. The semiconductor arrangement of claim 12 , the top surface of the semiconductor substrate from which the first fin nub protrudes disposed between a sidewall of the semiconductor substrate defining the first trench and a sidewall of the first fin nub.

14. The semiconductor arrangement of claim 12 , the semiconductor fin region comprising:
a second trench formed into the semiconductor substrate, the second trench formed between the first set of semiconductor fins and the second set of semiconductor fins.

15. The semiconductor arrangement of claim 12 , the first nub height less than a first fin height of a first fin within the first set of semiconductor fins.

16. The semiconductor arrangement of claim 12 , the semiconductor arrangement comprising:
a shallow trench isolation (STI) layer formed over the semiconductor fin region;
a gate oxide layer formed over the first set of semiconductor fins and the second set of semiconductor fins; and
a first gate structure formed over the gate oxide layer, the first gate structure formed over a first fin within the first set of semiconductor fins.

17. The semiconductor arrangement of claim 12 , the first pillar height less than a first fin height of a first fin within the first set of semiconductor fins.

18. The semiconductor arrangement of claim 12 , a first trench depth of the first trench less than a first fin height of a first fin within the first set of semiconductor fins.

19. A semiconductor arrangement, comprising:
a first semiconductor fin protruding from a substrate and having a first height;
a first semiconductor pillar protruding from the substrate and having a second height less than the first height;
a first semiconductor fin nub protruding from the substrate and having a third height less than the second height; and
a trench defined by the substrate and disposed between the first semiconductor pillar and the first semiconductor fin nub, wherein:
the first semiconductor pillar protrudes from a top surface of the substrate; and
the trench extends below the top surface of the substrate from which the first semiconductor pillar protrudes.

20. The semiconductor arrangement of claim 19 , comprising a shallow trench isolation (STI) layer overlaying the first semiconductor pillar and the first semiconductor fin nub, wherein a top surface of the first semiconductor fin protrudes above a top surface of the STI layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Tsung-Yu
• Chu-Hsuan Chen
• Kuang-Hsin Chen
• Chao Hsin-Lung

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title