Semiconductor device and formation thereof

Patent metadata

Field	Value
Publication number	US-9318488-B2
Application number	US-201414147851-A
Country	US
Kind code	B2
Filing date	Jan 6, 2014
Priority date	Jan 6, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first active region adjacent a first side of a shallow trench isolation (STI) region, the first active region comprising:
a first proximal fin adjacent the STI region and having a first proximal fin height, the first proximal fin being a first projection of a substrate; and
a first distal fin adjacent the first proximal fin and having a first distal fin height, the first distal fin being a second projection of the substrate, the first proximal fin height less than the first distal fin height, the first proximal fin disposed between the STI region and the first distal fin.

2. The semiconductor device of claim 1 , comprising:
a second active region adjacent a second side of the STI region, the second active region comprising:
a second proximal fin adjacent the STI region and having a second proximal fin height, the second proximal fin being a third projection of the substrate; and
a second distal fin adjacent the second proximal fin and having a second distal fin height, the second distal fin being a fourth projection of the substrate, the second proximal fin height less than the second distal fin height, the second proximal fin disposed between the STI region and the second distal fin.

3. The semiconductor device of claim 2 , comprising:
a metal connect in contact with the first distal fin, the first proximal fin, the second proximal fin and the second distal fin; and
an oxide disposed within the STI region and over a portion of the metal connect.

4. The semiconductor device of claim 3 , the oxide having an oxide height substantially equal to a difference between the first proximal fin height and the first distal fin height.

5. The semiconductor device of claim 2 , comprising an epitaxial (Epi) layer over the first proximal fin, the first distal fin, the second proximal fin and the second distal fin.

6. The semiconductor device of claim 1 , comprising a dielectric over the STI region.

7. The semiconductor device of claim 1 , the STI region comprising an oxide having an oxide volume that is inversely proportional to the first proximal fin height.

8. The semiconductor device of claim 7 , the oxide volume between about 1.1 to about 1.5 times greater than a second oxide volume of the oxide, where the second oxide volume corresponds to the first proximal fin having the first distal fin height.

9. The semiconductor device of claim 1 , comprising a gate over the first active region, the STI region and a second active region adjacent a second side of the STI region.

10. A semiconductor device comprising:
a first active region adjacent a first side of a shallow trench isolation (STI) region, the first active region comprising:
a first proximal fin adjacent the STI region and having a first proximal fin height, the first proximal fin being a first projection of a substrate; and
a first distal fin adjacent the first proximal fin and having a first distal fin height, the first distal fin being a second projection of the substrate, the first proximal fin height less than the first distal fin height, the first proximal fin disposed between the STI region and the first distal fin; and

a second active region adjacent a second side of the STI region, the second active region comprising:
a second proximal fin adjacent the STI region and having a second proximal fin height, the second proximal fin being a third projection of the substrate; and
a second distal fin adjacent the second proximal fin and having a second distal fin height, the second distal fin being a fourth projection of the substrate, the second proximal fin height less than the second distal fin height, the second proximal fin disposed between the STI region and the second distal fin.

11. The semiconductor device of claim 10 , a metal connect in contact with the first distal fin, the first proximal fin, the second proximal fin, and the second distal fin and extending through the STI region.

12. The semiconductor device of claim 10 , comprising an epitaxial (Epi) layer over the first proximal fin, the first distal fin, the second proximal fin and the second distal fin.

13. The semiconductor device of claim 12 , comprising a gate in contact with the Epi layer.

14. The semiconductor device of claim 10 , comprising a dielectric over the STI region.

15. A semiconductor device comprising:
a first active region having a first proximal fin, the first proximal fin being a first projection of a substrate;
a second active region having a second proximal fin, the second proximal fin being a second projection of the substrate;
a metal connect coupling a source/drain region of the first active region to a source/drain region of the second active region; and
a shallow trench isolation (STI) region between the first proximal fin and the second proximal fin, the metal connect extending through the STI region, the STI region comprising an oxide over a first portion of the metal connect, a top surface of the oxide co-planar with a top surface of a second portion of the metal connect.

16. The semiconductor device of claim 15 , the first proximal fin having a first proximal fin height and the first active region comprising:
a first distal fin having a first distal fin height, the first proximal fin height less than the first distal fin height, the first proximal fin disposed between the first distal fin and the STI region.

17. The semiconductor device of claim 16 , the metal connect in contact with the first proximal fin and the first distal fin.

18. The semiconductor device of claim 16 , the oxide having an oxide height substantially equal to a difference between the first proximal fin height and the first distal fin height.

19. The semiconductor device of claim 15 , comprising a gate extending over the oxide and coupled to the first active region and the second active region.

20. The semiconductor device of claim 15 , the metal connect in contact with the first proximal fin and the second proximal fin.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wu I-Wen
• Wang Mei-Yun
• Wang Hsien-Cheng
• Liu Shih-Wen
• Hsu Hsiao-Chiu
• Lin Hsin-Ying

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title