Memory device and method of manufacturing memory device

Patent metadata

Field	Value
Publication number	US-8963115-B2
Application number	US-201314017703-A
Country	US
Kind code	B2
Filing date	Sep 4, 2013
Priority date	Apr 12, 2013
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

According to one embodiment, a memory device includes a first conductive line extending in a first direction, second conductive lines each extending in a second direction intersect with the first direction, a third conductive line extending in a third direction intersect with the first and second directions, an insulating layer disposed between the second conductive lines and the third conductive line, resistance change elements each disposed on one of first and second surfaces of each of the second conductive lines in the third direction, and each connected to the third conductive line, a semiconductor layer connected between the first conductive line and one end of the third conductive line, and a select FET having a select gate electrode, and using the semiconductor layer as a channel.

First claim

What is claimed is:

1. A memory device comprising:
a first conductive line extending in a first direction;
second conductive lines each extending in a second direction which intersects with the first direction;
a third conductive line extending along in a third directions which is substantially perpendicular to the first and second directions, and one end of the third conductive line connecting to the first conductive line;
an insulating layer disposed between the second con…

Assignees

• Toshiba Kk

Inventors

• Murooka Kenichi

Classifications

• G11C2213/71

  Physics · mapped topic

• H01L45/04

  Electricity · mapped topic

• G11C13/0002

  Physics · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic