Memory device and method of controlling memory device

Patent metadata

Field	Value
Publication number	US-8971093-B2
Application number	US-201314025146-A
Country	US
Kind code	B2
Filing date	Sep 12, 2013
Priority date	May 14, 2013
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

According to one embodiment, a memory device includes a semiconductor layer connected between a first conductive line and one end of a third conductive line, resistance change elements connected between second conductive lines and the third conductive line respectively, a select FET having a select gate electrode, and using the semiconductor layer as a channel, and a control circuit executing a write/erase of at least one of the resistance change elements, and executing a recovering operation which adjusts a threshold voltage shift of the select FET after the write/erase.

First claim

What is claimed is:

1. A memory device comprising:
a first conductive line extending in a first direction;
second conductive lines each extending in a second direction intersect with the first direction;
a third conductive line extending in a third direction intersect with the first and second directions;
resistance change elements connected between the second conductive lines and the third conductive line respectively;
a semiconductor layer connected between the first con…

Assignees

• Toshiba Kk

Inventors

• Murooka Kenichi

Classifications

• G11C13/0069

  Physics · mapped topic

• G11C13/0097 Primary

  Physics · mapped topic

• G11C2213/71

  Physics · mapped topic

• G11C2213/77

  Physics · mapped topic

• H10N70/8833

  Electricity · mapped topic