Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-9505030-B2
Application number	US-201514689119-A
Country	US
Kind code	B2
Filing date	Apr 17, 2015
Priority date	Apr 18, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

First claim

What is claimed is:

1. A complementary metal oxide semiconductor (CMOS) wafer, comprising:
a semiconductor substrate;
an ultrasonic transducer comprising:
a cavity created by a partial removal of a first metallization layer of the CMOS wafer;
an electrode disposed between the cavity and the semiconductor substrate; and
an acoustic membrane comprising a dielectric layer and a second metallization layer of the CMOS wafer, the cavity being disposed between the semiconductor substrate and the acoustic membrane; and
an integrated circuitry in the semiconductor substrate, coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer;
wherein the electrode disposed between the cavity and the semiconductor substrate is a first electrode of the ultrasonic transducer, and wherein the ultrasonic transducer further comprises a second electrode disposed opposite the first electrode, the second electrode disposed in the acoustic membrane between the cavity and the second metallization layer.

2. The CMOS wafer of claim 1 , wherein the electrode disposed between the cavity and the semiconductor substrate comprises a liner layer of the partially removed first metallization layer.

3. The CMOS wafer of claim 1 , wherein the acoustic membrane comprises one or more conductive vias.

4. The CMOS wafer of claim 3 , wherein at least one of the one or more conductive vias of the acoustic membrane is electrically connected to the second electrode.

5. The CMOS wafer of claim 1 , further comprising at least one filled access hole passing through at least part of the acoustic membrane to the cavity.

6. The CMOS wafer of claim 1 , comprising a plurality of ultrasonic transducers including the ultrasonic transducer.

7. The CMOS wafer of claim 1 , wherein the second metallization layer is embedded within the dielectric layer of the acoustic membrane.

8. The CMOS wafer of claim 1 , further comprising at least one hole positioned to not pass through the acoustic membrane.

9. A complementary metal oxide semiconductor (CMOS) wafer, comprising:
a semiconductor substrate;
an ultrasonic transducer comprising:
a cavity created by a partial removal of a first metallization layer of the CMOS wafer;
an electrode disposed between the cavity and the semiconductor substrate; and
an acoustic membrane comprising a dielectric layer and a second metallization layer of the CMOS wafer, the cavity being disposed between the semiconductor substrate and the acoustic membrane; and
an integrated circuitry in the semiconductor substrate, coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer;
wherein the electrode disposed between the cavity and the semiconductor substrate is a bottom electrode of the ultrasonic transducer, and wherein the ultrasonic transducer further comprises a top electrode disposed in the acoustic membrane between the cavity and the second metallization layer, with the cavity being disposed between the bottom electrode and the top electrode, and wherein the bottom and top electrodes comprise liner layers of the partially removed first metallization layer.

10. A complementary metal oxide semiconductor (CMOS) wafer, comprising:
a semiconductor substrate;
a first metallization layer; and
an ultrasonic transducer comprising:
a cavity formed in the first metallization layer;
a first electrode disposed between the cavity and the semiconductor substrate, the first electrode comprising a first portion of the first metallization layer; and
an acoustic membrane comprising a dielectric layer, a second electrode, and a second metallization layer, the cavity being disposed between the semiconductor substrate and the acoustic membrane, the second electrode comprising a second portion of the first metallization layer, and disposed between the cavity and the second metallization layer; and
integrated circuitry in the semiconductor substrate, coupled to the ultrasonic transducer and configured to control operation of the ultrasonic transducer.

11. The complementary metal oxide semiconductor (CMOS) wafer of claim 10 , wherein the first metallization layer is configured to transmit electrical signals in a peripheral area of the substrate.

12. The complementary metal oxide semiconductor (CMOS) wafer of claim 10 , wherein the first metallization layer has a plurality of cavities formed therein, and wherein each cavity corresponds to a different ultrasonic transducer.

Assignees

• Butterfly Network Inc

Inventors

• Rothberg Jonathan M
• Fife Keith G
• Sanchez Nevada J
• Alie Susan A

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title