Structure of high electron mobility light emitting transistor

Patent metadata

Field	Value
Publication number	US-9502602-B2
Application number	US-201414587818-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Dec 31, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A structure of high electron mobility light emitting transistor comprises a substrate, a HEMT region disposed on the substrate, and a gallium nitride LED (GaN-LED) region disposed on the substrate. A two-dimensional electron gas layer is present in each of the HEMI region and the LED region, and the HEMT region is coupled to the LED region through the two-dimensional electron gas layer.

First claim

What is claimed is:

1. A structure of high electron mobility transistor (HEMT), the structure comprising:
a substrate;
a HEMT region disposed on the substrate; and
a light-emitting region disposed on the substrate,
wherein the light-emitting region does not have a n-type semiconductor layer on a barrier of the light-emitting region; a two-dimensional electron gas (2DEG) layer is present in each of the HEMT region and the light-emitting region, and the HEMT region is coupled to the light-emitting region through the 2DEG layer.

2. The structure according to claim 1 , further comprising:
a buffer layer disposed on the substrate;
wherein the barrier disposed on the buffer layer and partially covering the buffer layer; and
the HEMT region and the light-emitting region are disposed on the buffer layer, and the 2DEG layer is present between the buffer layer and the barrier.

3. The structure according to claim 2 , wherein:
the HEMT region comprises:
a gate layer directly or indirectly disposed on the barrier and partially covering the barrier; and
a source ohmic contact layer disposed on the buffer layer, partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier and partially covering the barrier; and
a drain ohmic contact layer disposed on the p-type semiconductor layer;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, and the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer.

4. The structure according to claim 2 , wherein
the structure further comprises a quantum well disposed between the buffer layer and the barrier;
the HEMT region comprises:
a gate layer disposed on the barrier; and
a source ohmic contact layer disposed on the buffer layer and partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier; and
a drain ohmic contact layer disposed on the p-type semiconductor layer;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer; and the 2DEG layer is present in the quantum well.

5. The structure according to claim 2 , wherein:
the HEMT region comprises:
a gate layer disposed on the barrier; and
a source ohmic contact layer disposed on the buffer layer, partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier; and
a drain ohmic contact layer disposed on the p-type semiconductor layer;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, and the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer.

6. The structure according to claim 2 , wherein:
the HEMT region comprises:
a gate layer disposed on the barrier;
a dielectric layer disposed between the gate layer and the barrier and partially covering the barrier; and
a source ohmic contact layer disposed on the buffer layer and partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier; and
a drain ohmic contact layer disposed on the p-type semiconductor layer;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, and the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer.

7. The structure according to claim 2 , wherein:
the HEMT region comprises:
a first barrier disposed on and covering the buffer layer;
a second barrier disposed on and covering the buffer layer;
a dielectric layer having a first portion, a second portion and a third portion, wherein the first portion is disposed on the buffer layer and the second portion and the third portion cover the first barrier and the second barrier, respectively;
a T-shaped gate layer disposed on the dielectric layer and partially covering the first portion, the second portion and the third portion; and
a source ohmic contact layer disposed on the buffer layer, wherein the source ohmic contact layer partially covers the buffer layer and contacts the first barrier and the second portion; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier; and
a drain ohmic contact layer disposed on the p-type semiconductor layer and the p-type semiconductor contacts the third portion;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, and the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer.

8. The structure according to claim 7 , wherein the T-shaped gate layer turns on a voltage or not to determine whether the 2DEG layer is present between the first portion and the buffer layer or not.

9. The structure according to claim 2 , wherein:
the HEMT region comprises:
a gate layer disposed on the barrier; and
a source ohmic contact layer disposed on the buffer layer and partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a quantum well disposed on the barrier;
a p-type semiconductor layer disposed on the quantum well; and
a drain ohmic contact layer disposed on the p-type semiconductor layer;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, and the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer.

10. A structure of high electron mobility transistor (HEMT), the structure comprising:
a substrate;
a HEMT region disposed on the substrate; and
a light-emitting region disposed on the substrate; and
a barrier disposed in the light-emitting region;
wherein there is not any n-type semiconductor layer on the barrier of the light-emitting region; a two-dimensional electron gas (2DEG) layer is present in each of the HEMT region and the light-emitting region, and the HEMT region is coupled to the light-emitting region through the 2DEG layer.

11. The structure according to claim 10 , further comprising:
a buffer layer disposed on the substrate;
the barrier disposed on the buffer layer and partially covering the buffer layer; and
the HEMT region comprises:
a gate layer directly or indirectly disposed on the barrier and partially covering the barrier; and
a source ohmic contact layer disposed on the buffer layer, partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier and partially covering the barrier; and
a drain ohmic contact layer disposed on the p-type semiconductor layer;
wherein a material of the drain ohmic contact layer is a metal or a metal oxide, and the gate layer is disposed between the source ohmic contact layer and the drain ohmic contact layer.

12. The structure according to claim 10 , further comprising:
a buffer layer disposed on the substrate;
the barrier disposed on the buffer layer and partially covering the buffer layer;
a quantum well disposed between the buffer layer and the barrier; and
the HEMT region comprises:
a gate layer disposed on the barrier; and
a source ohmic contact layer disposed on the buffer layer and partially covering the buffer layer and contacting the barrier; and
the light-emitting region comprises:
a p-type semiconductor layer disposed on the barrier; and
a drain ohmic cont

Assignees

• Nat Univ Tsing Hua

Inventors

• Huang Chih-Fang
• Li Yi-Chen
• Chang Ting-Fu
• Cheng Keh-Yung
• Wang Yu-Li
• Wu Chun-Hung
• Yang Wei-Chen
• Chiu Shao-Yen

Classifications

• H01L33/32

  Electricity · mapped topic

• H01L27/15

  Electricity · mapped topic

• H01L33/002 Primary

  Electricity · mapped topic

• H01L33/0041

  Electricity · mapped topic

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title