Backside coupled symmetric varactor structure

Patent metadata

Field	Value
Publication number	US-9502586-B1
Application number	US-201514853931-A
Country	US
Kind code	B1
Filing date	Sep 14, 2015
Priority date	Sep 14, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

First claim

What is claimed is:

1. A symmetric varactor structure, comprising:
a first varactor component having a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor, and a plurality of doped regions surrounding the body, the first varactor component supported on a backside by a front side surface of an isolation layer;
a second varactor component supported on the backside by the front side surface of the isolation layer; and
a backside conductive layer, electrically coupled to the backside of the first varactor component, and extending through the isolation layer and along a backside surface of the isolation layer, and through the backside surface to the front side surface of the isolation layer to electrically couple to the backside of the second varactor component.

2. The symmetric varactor structure of claim 1 , further comprising:
a signal port coupled to the gate; and
a plurality of control ports, each coupled to one of the plurality of doped regions, the signal port isolated from the plurality of control ports.

3. The symmetric varactor structure of claim 1 , in which a plate area of the first plate is modulated based on a bias voltage received from a control port to control the area modulating capacitor.

4. The symmetric varactor structure of claim 1 , in which the isolation layer comprises a buried oxide layer.

5. The symmetric varactor structure of claim 1 , in which the first varactor component and the second varactor component are integrated in an integrated circuit.

6. The symmetric varactor structure of claim 5 , in which the integrated circuit comprises a power amplifier (PA), an oscillator, an RF (radio frequency) tuner, an RF transceiver, a multiplexor and/or an RF circuit die.

7. The symmetric varactor structure of claim 1 , in which the first varactor component and the second varactor component are integrated in an RF (radio frequency) switch.

8. The symmetric varactor structure of claim 1 , in which the first varactor component and the second varactor component are supported by a substrate comprised of glass, quartz, or silicon.

9. The symmetric varactor structure of claim 1 , integrated into a radio frequency chip, the radio frequency chip incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

10. A symmetric varactor structure, comprising:
a first varactor component having a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor, and a plurality of doped regions surrounding the body, the first varactor component supported on a backside by a front side surface of an isolation layer;
a second varactor component supported on the backside by a second portion of the isolation layer; and
means for electrically coupling the backside of the second varactor component to the backside of the first varactor component by extending through the isolation layer and along a backside surface of the isolation layer, and through the backside surface to the front side surface of the isolation layer to electrically couple the backside of the second varactor component to the backside of the first varactor component.

11. The symmetric varactor structure of claim 10 , further comprising:
a signal port coupled to the gate; and
a plurality of control ports, each coupled to one of the plurality of doped regions, the signal port isolated from the plurality of control ports.

12. The symmetric varactor structure of claim 10 , in which a plate area of the first plate is modulated based on a bias voltage received from a control port to control the area modulating capacitor.

13. The symmetric varactor structure of claim 10 , in which the isolation layer comprises a buried oxide layer.

14. The symmetric varactor structure of claim 10 , in which the first varactor component and the second varactor component are integrated in an integrated circuit.

15. The symmetric varactor structure of claim 14 , in which the integrated circuit comprises a power amplifier (PA), an oscillator, an RF (radio frequency) tuner, an RF transceiver, a multiplexor and/or an RF circuit die.

16. The symmetric varactor structure of claim 14 , in which the first varactor component and the second varactor component are integrated in an RF (radio frequency) switch.

17. The symmetric varactor structure of claim 14 , in which the first varactor component and the second varactor component are supported by a substrate comprised of glass, quartz, or silicon.

18. The symmetric varactor structure of claim 14 , integrated into a radio frequency chip, the radio frequency chip incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

Assignees

• Qualcomm Inc

Inventors

• Kim Daeik Daniel
• Berdy David Francis
• Lan Je-Hsiung Jeffrey
• Yun Changhan Hobie
• Kim Jonghae

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10D1/64

  Variable-capacitance diodes, e.g. varactors · CPC title