Dual stack varactor

Patent metadata

Field	Value
Publication number	US-2016133758-A1
Application number	US-201614995329-A
Country	US
Kind code	A1
Filing date	Jan 14, 2016
Priority date	May 8, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common and may be electrically coupled to form a parallel varactor pair. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common. The parallel varactor pair may be advantageous in reducing die area for compound varactor circuits.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a lower contact layer positioned over the substrate; a lower varactor layer positioned over the lower contact layer and having a first doping profile; a common contact layer positioned over the lower varactor layer, wherein the lower contact layer, the lower varactor layer, and the common contact layer form a lower varactor; an upper varactor layer positioned over the common contact layer and having a second doping profile that is inverted with respect to the first doping profile; an upper contact layer positioned over the upper varactor layer, wherein the common contact layer, the upper varactor layer, and the upper contact layer form an upper varactor; and a first intra-connect structure electrically coupling the lower contact layer and the upper contact layer such that the lower varactor and the upper varactor are placed in parallel and form a first multi-varactor module.

2 . The semiconductor device of claim 1 wherein the common contact layer is a common anode layer for the upper and lower varactors.

3 . The semiconductor device of claim 1 wherein the common contact layer is a common cathode layer for the upper and lower varactors.

4 . The semiconductor device of claim 1 wherein the first intra-connect structure electrically couples to an upper ohmic contact positioned on the upper contact layer and electrically couples to a lower ohmic contact positioned on the lower contact layer.

5 . The semiconductor device of claim 1 wherein the first intra-connect structure is a surface metallization structure.

6 . The semiconductor device of claim 1 wherein the first intra-connect structure is a wire bond structure.

7 . The semiconductor device of claim 1 wherein the first and second doping profiles are one of an abrupt profile, hyper-abrupt profile, or linear doping profile.

8 . The semiconductor device of claim 1 wherein the lower varactor layer resides over a first area and the upper varactor layer resides over a second area, and the second area is between 25% and 50% of the first area.

9 . The semiconductor device of claim 1 wherein the lower varactor layer resides over a first area and the upper varactor layer resides over a second area, and the second area is between 50% and 95% of the first area.

10 . The semiconductor device of claim 1 wherein the common contact layer includes an upper common contact layer directly coupled with the upper varactor layer, and a lower common contact layer directly coupled with the lower varactor layer, and a common etch stop layer positioned between and directly coupled with the upper common contact layer and the lower common contact layer.

11 . The semiconductor device of claim 1 wherein the lower contact layer comprises a top lower contact layer directly coupled with the lower varactor layer, and a bottom lower contact layer directly coupled with the substrate, and a lower etch stop layer directly coupled with and positioned between the top lower contact layer and the bottom lower contact layer.

12 . The semiconductor device of claim 1 further comprising a second multi-varactor module positioned over the substrate and adjacent to the first multi-varactor module, wherein the first multi-varactor module is electrically coupled with the second multi-varactor module.

13 . The semiconductor device of claim 1 wherein the upper and lower varactor layers are n− doped.

14 . The semiconductor device of claim 2 wherein the common anode layer is p+ doped.

15 . The semiconductor device of claim 3 wherein the common cathode layer is n+ doped.

16 . The semiconductor device of claim 14 wherein the upper and lower contact layers are n+ doped.

17 . The semiconductor device of claim 15 wherein the upper and lower contact layers are p+ doped.

18 . The semiconductor device of claim 11 wherein adjacent layers of the first and second multi-varactor modules have essentially the same composition.

19 . The semiconductor device of claim 1 further comprising a resistor coupled to the first intra-connect structure.

20 . A semiconductor device comprising:
a substrate; a first multi-varactor module comprising:
a first lower contact layer positioned over the substrate;
a first lower varactor layer positioned over the first lower contact layer and having a first doping profile;
a first common contact layer positioned over the first lower varactor layer, wherein the first lower contact layer, the first lower varactor layer, and the first common contact layer form a first lower varactor;
a first upper varactor layer positioned over the first common contact layer and having a second doping profile that is inverted with respect to the first doping profile;
a first upper contact layer positioned over the first upper varactor layer, wherein the first common contact layer, the first upper varactor layer, and the first upper contact layer form a first upper varactor; and
a first intra-connect structure electrically coupling the first lower contact layer and the first upper contact layer such that the first lower varactor and the first upper varactor are placed in parallel and form a first multi-varactor module;
a second multi-varactor module comprising:
a second lower contact layer positioned over the substrate;
a second lower varactor layer positioned over the second lower contact layer and having the first doping profile;
a second common contact layer positioned over the second lower varactor layer, wherein the second lower contact layer, the second lower varactor layer, and the second common contact layer form a second lower varactor;
a second upper varactor layer positioned over the second common contact layer and having the second doping;
a second upper contact layer positioned over the second upper varactor layer, wherein the second common contact layer, the second upper varactor layer, and the second upper contact layer form a second upper varactor; and
a second intra-connect structure electrically coupling the second lower contact layer and the second upper contact layer such that the second lower varactor and the second upper varactor are placed in parallel and form a second multi-varactor module; and
an inter-connect structure electrically coupling the first and second multi-varactor modules.

Assignees

• Triquint Semiconductor Inc

Inventors

• Wright Peter V

Classifications

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D1/045

  of capacitors having potential barriers, e.g. varactors · CPC title

• H10D84/215

  of only varactors · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D1/64 Primary

  Variable-capacitance diodes, e.g. varactors · CPC title