Multi-gate and complementary varactors in FinFET process

Patent metadata

Field	Value
Publication number	US-9299699-B2
Application number	US-201313801089-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.

First claim

What is claimed is:

1. A varactor comprising:
at least one semiconductor fin;
a first gate; and
a second gate physically disconnected from the first gate, wherein the first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin, and wherein source and drain regions of the first FinFET and the second FinFET are constantly electrically shorted with each other to form the varactor.

2. The varactor of claim 1 , wherein first FinFET and the second FinFET do not share fins.

3. The varactor of claim 1 , wherein the first FinFET and the second FinFET comprise a same fin.

4. The varactor of claim 1 , wherein the first gate is connected to a second source and a second drain of the second FinFET, and wherein the second gate is connected to a first source and a first drain of the first FinFET.

5. The varactor of claim 1 , wherein the at least one semiconductor fin comprises a semiconductor fin, wherein the first gate forms the first FinFET with a first sidewall portion of the semiconductor fin, and wherein the second gate forms the second FinFET with a second sidewall portion of the semiconductor fin.

6. The varactor of claim 5 , wherein the first gate and the second gate are electrically decoupled from each other, and the varactor further comprises a gate dielectric comprising:
a first sidewall portion between and in physical contact with both the first gate and the first sidewall portion of the semiconductor fin; and
a second sidewall portion between and in physical contact with both the second gate and the second sidewall portion of the semiconductor fin.

7. The varactor of claim 6 , wherein the gate dielectric further comprises a top portion connecting the first sidewall portion of the gate dielectric to the second sidewall portion of the gate dielectric.

8. A varactor comprising:
a first semiconductor fin;
a first gate dielectric comprising:
a first sidewall portion on a first sidewall of the first semiconductor fin; and
a second sidewall portion on a second sidewall of the first semiconductor fin;

a first gate in contact with the first sidewall portion of the first gate dielectric, wherein the first gate, the first sidewall portion of the first gate dielectric, and the first sidewall of the first semiconductor fin form portions of a first varactor; and
a second gate in contact with the second sidewall portion of the first gate dielectric, wherein the second gate is physically disconnected from the first gate, and wherein the second gate, the second sidewall portion of the first gate dielectric, and the second sidewall of the first semiconductor fin form portions of a second varactor; and
a source and a drain region on opposite ends of the first gate dielectric, wherein the source and the drain regions are interconnected to form the first varactor and the second varactor.

9. The varactor of claim 8 , wherein the first gate and the second gate are electrically disconnected from each other.

10. The varactor of claim 8 further comprising:
a second semiconductor fin parallel to the first semiconductor fin; and
a second gate dielectric on sidewalls and a top surface of the second semiconductor fin, wherein the first gate further extends over the second gate dielectric.

11. The varactor of claim 8 , wherein the first gate dielectric further comprises a top surface portion overlapping the first semiconductor fin, and wherein the first gate and the second gate does not overlap the top surface portion.

12. A varactor comprising:
a first FinFET comprising:
a plurality of semiconductor fins;
a first gate over the plurality of semiconductor fins; and
a first source and a first drain comprising end portions of the plurality of semiconductor fins, wherein the first source is electrically connected to the first drain; and

a second FinFET connected to the first FinFET to form the varactor, wherein the second FinFET comprises:
at least one semiconductor fin;
a second gate over the at least one semiconductor fin; and
a second source and a second drain comprising end portions of the at least one semiconductor fin, wherein the second source is electrically connected to the second drain, and wherein a first total number of fins in the first FinFET is greater than a second total number of fins in the second FinFET.

13. The varactor of claim 12 , wherein the first gate is connected to the second source and the second drain, and wherein the second gate is connected to the first source and the first drain.

14. The varactor of claim 13 , wherein the first source, the first drain, the second source, and the second drain are of a same conductivity type.

15. The varactor of claim 12 , wherein the first gate is connected to the second gate, and wherein the first source, the first drain, the second source, and the second drain are interconnected.

16. The varactor of claim 15 , wherein the first source and the first drain are of a first conductivity type, and wherein the second source and the second drain are of a second conductivity type opposite to the first conductivity type.

17. The varactor of claim 15 , wherein the first source and the second source are of a first conductivity type, and wherein the first drain and second drain are of a second conductivity type opposite to the first conductivity type.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lin Chi-Hsien
• Lu Ying-Ta
• Liao Hsien-Yuan
• Chen Ho-Hsiang
• Jou Chewn-Pu
• Hsueh Fu-Lung

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title