Method and system for wafer level singulation

US9502294B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9502294-B2
Application numberUS-201314075603-A
CountryUS
Kind codeB2
Filing dateNov 8, 2013
Priority dateFeb 18, 2011
Publication dateNov 22, 2016
Grant dateNov 22, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for singulation of a plurality of semiconductor dies, the system comprising: a coating unit configured to: receive an identification of defective devices; from a continuous film on a semiconductor substrate; remove an edge portion of the continuous film; remove one or more central portions of the continuous film to form a remaining film, the one or more central portions being associated with the defective devices; coat the edge portion with an adhesive material; and form a patchwork of adhesive locations distributed across the semiconductor substrate by coating the one or more central portions with the adhesive material; a bonding unit configured to join the patchwork of adhesive locations and the remaining film on the semiconductor substrate to a carrier substrate; wherein the coating unit is further configured to form a mask layer on the semiconductor substrate; a laser processing unit configured to expose a predetermined portion of the mask layer to laser light; a development processing unit configured to form a predetermined mask pattern on the semiconductor substrate; a singulation unit configured to for the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask; and a die separation unit configured to separate at least a subset of the plurality of semiconductor dies from the carrier substrate. 2. The system of claim 1 wherein the carrier substrate comprises a silicon substrate. 3. The system of claim 1 wherein the coating unit includes an edge bead removal (EBR) arm. 4. The system of claim 1 wherein the continuous film comprises an inert material. 5. The system of claim 4 wherein the inert material comprises an amorphous carbon material. 6. The system of claim 1 wherein the at least a subset of the plurality of semiconductor dies are not positioned at the one or more central portions. 7. The system of claim 1 wherein the singulation unit comprises a development unit and an etching unit. 8. The system of claim 1 wherein the laser processing unit comprises a laser source. 9. The system of claim 1 further comprising a cleaning unit. 10. The system of claim 1 wherein the laser processing unit, the development processing unit, and the singulation unit are a single unit.

Assignees

Inventors

Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • used during dicing or grinding · CPC title

  • Wafer tapes, e.g. grinding or dicing support tapes · CPC title

  • comprising a chamber adapted to a particular process · CPC title

  • Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9502294B2 cover?
A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined por…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).