Circuit substrate, semiconductor package and process for fabricating the same

Patent metadata

Field	Value
Publication number	US-9497864-B2
Application number	US-201313898486-A
Country	US
Kind code	B2
Filing date	May 21, 2013
Priority date	Mar 26, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

First claim

What is claimed is:

1. A circuit substrate, comprising:
a stacked circuit structure having a first surface and a second surface opposite to the first surface;
a first patterned inner conductive layer disposed on the first surface and having a plurality of first pads;
a first patterned outer conductive layer disposed on the first patterned inner conductive layer and having a plurality of first conductive pillars, wherein each of the first conductive pillars is located on the corresponding first pad;
a first dielectric layer covering the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer and having a plurality of first concaves, wherein each of the first concaves exposes a top and a side of the corresponding first conductive pillar, and the top and the side of the first conductive pillar are exposed for directly soldering a chip;
a second patterned inner conductive layer disposed on the second surface and having a plurality of second pads;
a second patterned outer conductive layer disposed on the second patterned inner conductive layer and having a plurality of second conductive pillars, wherein each of the second conductive pillars is located on the corresponding second pad; and
a second dielectric layer covering the second surface, the second patterned inner conductive layer and the second patterned outer conductive layer and having a plurality of second concaves, wherein each of the second concaves exposes a top and a side of the corresponding second conductive pillar;
wherein an outer diameter of each of the second conductive pillars is greater than an outer diameter of the corresponding second pad, and the corresponding second concave exposes a portion of the corresponding second pad.

2. The circuit substrate as claimed in claim 1 , wherein a height of the first dielectric layer relative to the first surface is greater than a height of each of the first conductive pillars relative to the first surface.

3. The circuit substrate as claimed in claim 1 , wherein the adjacent first concaves overlap one another and a sub-concave is formed therebetween.

4. The circuit substrate as claimed in claim 1 , wherein a height of the second dielectric layer relative to the second surface is greater than a height of each of the second conductive pillars relative to the second surface.

5. The circuit substrate as claimed in claim 1 , wherein the first patterned inner conductive layer has at least one first inner conductive pattern, the first patterned outer conductive layer has at least one first outer conductive pattern, and the first inner conductive pattern and the first outer conductive pattern serve as a heat dissipating path.

6. The circuit substrate as claimed in claim 1 , wherein the first patterned inner conductive layer has at least one first inner conductive pattern, the first patterned outer conductive layer has at least one first outer conductive pattern, and the first inner conductive pattern and the first outer conductive pattern serve as a reference plane.

7. A semiconductor package, comprising:
a circuit substrate, comprising:
a stacked circuit structure having a first surface and a second surface opposite to the first surface;
a first patterned inner conductive layer disposed on the first surface and having a plurality of first pads;
a first patterned outer conductive layer disposed on the first patterned inner conductive layer and having a plurality of first conductive pillars, wherein each of the first conductive pillars is located on the corresponding first pad;
a first dielectric layer covering the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer and having a plurality of first concaves, wherein each of the first concaves exposes a top and a side of the corresponding first conductive pillar;
a second patterned inner conductive layer disposed on the second surface and having a plurality of second pads;
a second patterned outer conductive layer disposed on the second patterned inner conductive layer and having a plurality of second conductive pillars, wherein each of the second conductive pillars is located on the corresponding second pad; and
a second dielectric layer covering the second surface, the second patterned inner conductive layer and the second patterned outer conductive layer and having a plurality of second concaves, wherein each of the second concaves exposes a top and a side of the corresponding second conductive pillar;
wherein an outer diameter of each of the second conductive pillars is greater than an outer diameter of the corresponding second pad, and the corresponding second concave exposes a portion of the corresponding second pad; and

a chip soldered to the first conductive pillars.

8. The semiconductor package as claimed in claim 7 , wherein a height of the first dielectric layer relative to the first surface is greater than a height of each of the first conductive pillars relative to the first surface.

9. The semiconductor package as claimed in claim 7 , further comprising:
a heat spreader, the first patterned inner conductive layer having at least one first inner conductive pattern, the first patterned outer conductive layer having at least one first outer conductive pattern, the first outer conductive pattern being located on the first inner conductive pattern, the first dielectric layer exposing the first outer conductive pattern, wherein the first inner conductive pattern and the first outer conductive pattern serve as a heat dissipating path, and the heat spreader is soldered to the first outer conductive pattern.

10. The semiconductor package as claimed in claim 7 , wherein the adjacent first concaves overlap one another and a sub-concave is formed therebetween.

11. The semiconductor package as claimed in claim 7 , wherein a height of the second dielectric layer relative to the second surface is greater than a height of each of the second conductive pillars relative to the second surface.

12. The semiconductor package as claimed in claim 7 , further comprising:
a heat slug, the second patterned inner conductive layer having at least one second inner conductive pattern, the second patterned outer conductive layer having at least one second outer conductive pattern, the second outer conductive pattern being located on the second inner conductive pattern, the second dielectric layer exposing the second outer conductive pattern, wherein the second inner conductive pattern and the second outer conductive pattern serve as a heat dissipating path, and the heat slug is soldered to the second outer conductive pattern.

Assignees

• Via Tech Inc

Inventors

• Kung Chen-Yueh

Classifications

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title