Silicon carbide static induction transistor and process for making a silicon carbide static induction transistor

Patent metadata

Field	Value
Publication number	US-9490355-B2
Application number	US-201514945936-A
Country	US
Kind code	B2
Filing date	Nov 19, 2015
Priority date	Nov 12, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

First claim

What is claimed is:

1. A static induction transistor (SIT), comprising:
a silicon carbide substrate doped with a first conductivity type and including a plurality of first recessed regions in a top surface of the silicon carbide substrate;
a plurality of epitaxial gate regions within the first recessed regions having an in situ second conductivity type dopant;
a plurality of epitaxial channel regions positioned between adjacent epitaxial gate regions having an in situ first conductivity type dopant; and
a plurality of epitaxial source regions on said plurality of epitaxial channel regions having an in situ first conductivity type dopant.

2. The SIT of claim 1 , wherein the plurality of epitaxial gate regions are configured as gate fingers, and further comprising a gate lead which is electrically coupled to the gate fingers.

3. The SIT of claim 2 , wherein the silicon carbide substrate further includes a second recessed region in the top surface of the silicon carbide substrate, and wherein the gate lead comprises an epitaxial gate lead region within the second recessed region having an in situ second conductivity type dopant.

4. The SIT of claim 3 , further comprising a dielectric layer overlying the plurality of epitaxial source regions and covering the epitaxial gate lead region, the dielectric layer including a gate contact opening filled with a metal material to form a gate contact to the gate lead region.

5. The SIT of claim 1 , wherein the silicon carbide substrate further includes an additional recessed region in the top surface of the silicon carbide substrate, further comprising an epitaxial guard region within the additional recessed region having an in situ second conductivity type dopant.

6. The SIT of claim 5 , wherein the guard region forms a guard ring.

7. The SIT of claim 1 , wherein the silicon carbide substrate further includes a plurality of second recessed regions in a bottom surface of the silicon carbide substrate, said second recessed regions being vertically aligned with the epitaxial channel regions positioned between adjacent epitaxial gate regions.

8. The SIT of claim 7 , further comprising a silicide material formed in said plurality of second recessed regions.

9. The SIT of claim 1 , further comprising a silicide material formed on each of the plurality of epitaxial source regions.

10. The SIT of claim 1 , wherein the plurality of epitaxial source regions further extend to cover over the plurality of epitaxial gate regions.

11. The SIT of claim 1 , further comprising a dielectric layer overlying the plurality of epitaxial source regions, the dielectric layer including a plurality of source contact openings filled with a metal material to form source contacts.

12. A static induction transistor (SIT), comprising:
a first layer of silicon carbide doped with a first conductivity type dopant to form a drain region and including a plurality of first recesses in a top surface of said first layer of silicon carbide;
a gate region within each first recess, said gate region formed by epitaxial silicon carbide doped with a second conductivity type dopant;
a channel region positioned between adjacent gate regions, said channel region formed by epitaxial silicon carbide doped with the first conductivity type dopant; and
a second layer of silicon carbide doped with the first conductivity type dopant overlying the gate regions to form a source region.

13. The SIT of claim 12 , wherein each gate regions defines a gate finger, and further comprising a gate lead which is electrically coupled to the gate fingers and formed by epitaxial silicon carbide doped with the second conductivity type dopant.

14. The SIT of claim 13 , further comprising a dielectric layer overlying the second layer, the dielectric layer including a gate contact opening filled with a metal material to form a gate contact to the gate lead.

15. The SIT of claim 12 , wherein the first layer of silicon carbide further includes an additional recess in the top surface of said first layer of silicon carbide, further comprising a guard region within the additional recess formed by semiconductor material doped with the second conductivity type dopant.

16. The SIT of claim 15 , wherein the semiconductor material is silicon carbide.

17. The SIT of claim 15 , wherein the additional recess has a ring shape substantially surrounding the first recesses and the guard region forms a guard ring.

18. The SIT of claim 12 , further comprising a dielectric layer overlying the second layer, the dielectric layer including a source contact opening filled with a metal material to form a source contact to the source region.

19. The SIT of claim 12 , further comprising a third layer of silicon carbide underneath the first layer of silicon carbide, wherein the third layer of silicon carbide includes a plurality of second recesses in a bottom surface of the third layer of silicon carbide, each second recess being vertically aligned with one of the channel regions.

20. The SIT of claim 19 , further comprising a silicide material formed in said plurality of second recesses.

21. The SIT of claim 12 , further comprising a silicide material formed on said source region.

22. A static induction transistor (SIT), comprising:
a silicon carbide substrate doped with a first conductivity type dopant at a first dopant concentration to form a drain region and including a plurality of first recesses in a top surface of said silicon carbide substrate;
a gate region within each first recess, said gate region formed by epitaxial silicon carbide doped with a second conductivity type dopant;
a channel region positioned between adjacent gate regions, said channel region formed by epitaxial silicon carbide doped with the first conductivity type dopant at a second dopant concentration less than said first dopant concentration; and
a source region positioned between adjacent gate regions over each channel region and formed by epitaxial silicon carbide doped with the first conductivity type dopant at a third dopant concentration more than said second dopant concentration.

23. The SIT of claim 22 further comprising a silicide material on each source region and a silicide material on a bottom surface of the silicon carbide substrate.

24. The SIT of claim 22 , wherein the third dopant concentration is more than the first dopant concentration.

Assignees

• St Microelectronics Inc

Inventors

• Morin Pierre
• Zhang John Hongguang

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10D64/0115

  to silicon carbide · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title