Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process

Patent metadata

Field	Value
Publication number	US-9490344-B2
Application number	US-201213345922-A
Country	US
Kind code	B2
Filing date	Jan 9, 2012
Priority date	Jan 9, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.

First claim

What is claimed:

1. A method of forming a metal silicide region on a source/drain region of a transistor, wherein said metal silicide region has a target thickness, the method comprising:
forming an upper portion of said source/drain region that is positioned above an uppermost surface of a semiconducting substrate, said upper portion of said source/drain region having an upper surface that is positioned above said uppermost surface of said substrate by a distance that is at least equal to said target thickness of said metal silicide region; and
forming said metal silicide region in a portion of said upper portion of said source/drain region, wherein said metal silicide region has a bottom surface positioned above said uppermost surface of said substrate.

2. The method of claim 1 , further comprising introducing a dopant material into said source/drain region.

3. The method of claim 1 , Wherein forming said upper portion of said source/drain region above said uppermost surface of said semiconducting substrate comprises performing an epitaxial deposition process to form at least said upper portion of said source/drain region.

4. The method of claim 1 , wherein forming said upper portion of said source/drain region above said uppermost surface of said semiconducting substrate comprises performing an epitaxial deposition process to form an undoped upper portion of said source/drain region.

5. The method of claim 4 , further comprising performing an ion implantation process to introduce a dopant material into said undoped upper portion of said source/drain region.

6. The method of claim 1 , wherein forming said upper portion of said source/drain region above said uppermost surface of said semiconducting substrate comprises performing an epitaxial deposition process to form a doped upper portion of said source/drain region.

7. A method of forming a metal silicide region on a source/drain region of a transistor, wherein said metal silicide region has a target thickness, the method comprising:
forming an extension implant region and a source/drain implant region in a Semiconducting substrate proximate a gate structure of said transistor;
after forming said extension implant region and said source/drain implant region, performing an epitaxial deposition process to form a semiconductor material positioned above said source/drain implant region and an uppermost surface of said semiconducting substrate, said semiconductor material having an upper surface that is positioned above said uppermost surface of said substrate by a distance that is at least equal to said target thickness of said metal silicide region; and
forming said metal silicide region in a portion of said semiconductor material wherein said metal silicide region has a bottom surface positioned above said uppermost surface of said substrate.

8. The method of claim 7 , wherein prior to performing said epitaxial deposition process, performing a first activation anneal process to activate dopant materials in said extension implant region and said source/drain implant region.

9. The method of claim 8 , wherein performing said epitaxial deposition process to form .said semiconductor material comprises performing said epitaxial deposition Process while introducing a dopant material in situ to form a doped semiconductor material.

10. The method of claim 9 , wherein after performing said epitaxial deposition process to form said semiconductor material, performing a second activation anneal process to reactivate dopant materials in at least said extension implant region and said source/drain implant region.

11. The method of claim 8 , wherein, prior to forming said metal silicide region, forming a stress inducing layer of material on said semiconductor material.

12. A method of forming a metal silicide region on a source/drain region of a transistor, wherein said metal silicide region has a target thickness, the method comprising:
forming an extension implant region and a source/drain implant region in a semiconducting substrate proximate a gate structure of said transistor;
performing a first activation anneal process to activate dopant materials in said extension implant region and said source/drain implant region;
after performing said first activation anneal process, performing an epitaxial deposition process to form a doped semiconductor material positioned above said source/drain implant region and an uppermost surface of said semiconducting substrate, said semiconductor material having an upper surface that is positioned above said uppermost surface of said substrate by a distance that is at least equal to said target thickness of said metal silicide region; and
forming said metal silicide region in a portion of said doped semiconductor material wherein said metal silicide region has a bottom surface positioned above said uppermost surface of said substrate.

13. The method of claim 12 , wherein, prior to forming said doped semiconductor material, forming a stress inducing layer of material on said surface of said substrate.

14. The method of claim 12 , wherein after performing said epitaxial deposition process to form said doped semiconductor material, performing a second activation anneal process to reactivate dopant materials in at least said extension implant region and said source/drain implant region.

15. A method of forming a metal silicide region on a source/drain region of a transistor, wherein said metal silicide region has a target thickness, the method comprising:
forming an extension implant region in a semiconducting substrate proximate a gate structure of said transistor;
after forming said extension implant region, forming a cavity in said substrate proximate . said gate structure of said transistor;
performing an epitaxial deposition process to form an undoped Semiconductor material in said cavity, said undoped semiconductor material having an upper surface that is positioned above said an uppermost surface of said substrate by a distance that is at least equal to said target thickness of said metal silicide region;
performing an ion implantation process to introduce a dopant material into said semiconductor material and to form a source/drain implant region;
after performing said ion implantation process, performing an activation anneal process to activate dopant materials in at least said extension implant region and said source/drain implant region; and
after performing said activation anneal process, forming said metal silicide region in a portion of said semiconductor material such that a bottom surface of said metal silicide re ion is positioned above said upper surface of said semiconductor material and the uppermost surface of said semiconductor material is positioned above said uppermost surface of said substrate.

16. The method of claim 15 , wherein, after performing said ion implantation process, but prior to forming said metal silicide region, forming a stress inducing layer of material on said semiconductor material.

Assignees

• Flachowsky Stefan
• Hoentschel Jan
• Scheiper Thilo
• Globalfoundries Inc

Inventors

• Flachowsky Stefan
• Hoentschel Jan
• Scheiper Thilo

Classifications

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/796

  having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates · CPC title