Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process
US-9490344-B2 · Nov 8, 2016 · US
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Hoentschel Jan patents
Hoentschel Jan holds 9 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 9 |
| Recent patents | 0 |
| First publication | Jan 20, 2015 |
| Latest publication | Nov 8, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Graded well implantation for asymmetric transistors having reduced gate electrode pitches
US-9449826-B2 · Sep 20, 2016 · US
Replacement gate FinFET structures with high mobility channel
US-9224840-B2 · Dec 29, 2015 · US
Contact bars with reduced fringing capacitance in a semiconductor device
US-9184095-B2 · Nov 10, 2015 · US
Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
US-9093554-B2 · Jul 28, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process
US-9490344-B2 · Nov 8, 2016 · US
Graded well implantation for asymmetric transistors having reduced gate electrode pitches
US-9449826-B2 · Sep 20, 2016 · US
Replacement gate FinFET structures with high mobility channel
US-9224840-B2 · Dec 29, 2015 · US
Contact bars with reduced fringing capacitance in a semiconductor device
US-9184095-B2 · Nov 10, 2015 · US
Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
US-9093554-B2 · Jul 28, 2015 · US
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 9 |