Stress memorization techniques for transistor devices
US-2015364570-A1 · Dec 17, 2015 · US
having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates
having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10D30/796 |
| Official title | {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates} |
| Display label | having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates |
| Total patents | 439 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 69 |
| 2016 | 88 |
| 2017 | 75 |
| 2018 | 45 |
| 2019 | 37 |
| 2020 | 26 |
| 2021 | 26 |
| 2022 | 21 |
| 2023 | 15 |
| 2024 | 10 |
| 2025 | 23 |
| 2026 | 4 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Mechanisms for forming semiconductor device having stable dislocation profile
US-9214514-B2 · Dec 15, 2015 · US
Method of manufacturing semiconductor devices
US-9214395-B2 · Dec 15, 2015 · US
Method for manufacturing semiconductor structure
US-9202913-B2 · Dec 1, 2015 · US
Method and Apparatus For Enhancing Channel Strain
US-2015340293-A1 · Nov 26, 2015 · US
Forming independent-gate finfet with tilted pre-amorphization implantation and resulting device
US-2015340501-A1 · Nov 26, 2015 · US
Integrated circuits with stressed semiconductor-on-insulator (SOI) body contacts and methods for fabricating the same
US-9196544-B2 · Nov 24, 2015 · US
FinFET device having a strained region
US-9177801-B2 · Nov 3, 2015 · US
Method to co-integrate oppositely strained semiconductor devices on a same substrate
US-2015303218-A1 · Oct 22, 2015 · US
Microwave Anneal (MWA) for Defect Recovery
US-2015294881-A1 · Oct 15, 2015 · US
Dislocation Stress Memorization Technique (DSMT) on Epitaxial Channel Devices
US-2015295085-A1 · Oct 15, 2015 · US
Integrated circuits with stressed semiconductor substrates and processes for preparing integrated circuits including the stressed semiconductor substrates
US-2015287824-A1 · Oct 8, 2015 · US
Formation of Dislocations in Source and Drain Regions of FinFET Devices
US-2015270342-A1 · Sep 24, 2015 · US
Curved Wafer Processing Method and Apparatus
US-2015270153-A1 · Sep 24, 2015 · US
Integrated circuits with stressed semiconductor-on-insulator (soi) body contacts and methods for fabricating the same
US-2015262885-A1 · Sep 17, 2015 · US
Device and method for fabricating thin semiconductor channel and buried strain memorization layer
US-2015255603-A1 · Sep 10, 2015 · US
Encapsulation of closely spaced gate electrode structures
US-9123568-B2 · Sep 1, 2015 · US
Re-crystallization for boosting stress in mos device
US-2015243526-A1 · Aug 27, 2015 · US
Methods for Forming Semiconductor Device Structures
US-2015243788-A1 · Aug 27, 2015 · US
Pinch-off control of gate edge dislocation
US-9117844-B2 · Aug 25, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10D30/796?
- CPC H10D30/796 is the Cooperative Patent Classification code for “having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates.”
- How many patents are filed under CPC H10D30/796 (having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates)?
- Our database includes 439 publications tagged with this CPC code.
- Is patent activity under CPC H10D30/796 growing?
- Publication counts under this code: 10 in 2024 vs 23 in 2025 (latest complete years).