Reliable interconnect integration scheme

Patent metadata

Field	Value
Publication number	US-9490165-B2
Application number	US-98286210-A
Country	US
Kind code	B2
Filing date	Dec 30, 2010
Priority date	Dec 30, 2010
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.

First claim

What is claimed is:

1. A method of forming a device comprising:
providing a substrate prepared with a dielectric layer; and
processing the dielectric layer to serve as an intermetal dielectric (IMD) layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values, wherein processing the dielectric layer comprises
providing a second dielectric material having a second k value,
forming interconnects in the second dielectric material,
depositing a passivation layer covering the second dielectric material and surface of the interconnects after forming the interconnects,
patterning the passivation layer to cover only top surfaces of the interconnects,
providing a patterned soft mask layer covering the patterned passivation layer and in direct contact with a portion of the second dielectric material adjacent to the passivation layer and interconnects,
removing exposed portions of the second dielectric material not covered by the patterned soft mask layer to form openings,
providing a first dielectric material to fill the openings and between the interconnects, wherein the first dielectric material comprises a first k value which is lower than the second k value, and wherein the second dielectric material surrounds and contacts sides and bottom surface of the first dielectric material, and
processing the first and second dielectric materials such that top surfaces of the first dielectric material, the second dielectric material and the interconnects are coplanar with each other.

2. The method of claim 1 wherein the second dielectric material comprises a low k (LK) dielectric material and the first dielectric material comprises an ultra low k (ULK) dielectric material.

3. The method of claim 2 wherein the LK material comprises SiOCH and the ULK material comprises pSiCOH.

4. The method of claim 1 wherein:
the hybrid IMD layer comprises a third dielectric material with a third k value; and
the first dielectric material comprises the lowest k value, the second dielectric material comprises an intermediate k value, and the third dielectric material comprises a normal k value.

5. The method of claim 4 wherein the first dielectric material comprises an ULK material, the second dielectric material comprises a LK material, and the third dielectric material comprises a normal k (NK) material.

6. The method of claim 5 wherein the ULK material comprises pSiCOH, the LK material comprises SiOCH, and the NK material comprises SiO2 or FSG.

7. The method of claim 4 wherein the hybrid IMD layer comprises a fourth material having a different k value than the first, second and third dielectric materials.

8. The method of claim 1 wherein processing the first and second dielectric materials comprises removing excess first dielectric material by a planarization process, wherein the planarizing process also removes the passivation layer which covers only the top surfaces of the interconnects.

9. A method of forming a device comprising:
providing a substrate prepared with a dielectric layer; and
processing the dielectric layer to serve as an intermetal dielectric (IMD) layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values, the hybrid IMD layer comprises
a first dielectric material with a first k value,
a second dielectric material with a second k value,
a third dielectric material with third k value, and
a fourth material having a different k value than the first, second and third dielectric materials, and
interconnects disposed in the second dielectric material, wherein
the fourth material comprises the lowest k value among the first, second and third dielectric materials,
the second dielectric material surrounds sides and bottom of the first dielectric material, and
top surfaces of the first dielectric material, the second dielectric material and the interconnects are coplanar with each other.

10. The method of claim 9 wherein the fourth material comprises air.

11. A method of forming a device comprising:
providing a substrate prepared with a dielectric layer;
processing the dielectric layer to serve as an intermetal dielectric (IMD) layer, wherein the IMD layer comprises at least a trench in a trench level, a via in a via level, a first dielectric material having a first k value and a second dielectric material comprising a second k value, wherein
the second dielectric material lines sidewalls and a bottom of the trench in the trench level and sidewalls of the via in the via level and a bottom of the IMD layer, and
the IMD layer comprises a third dielectric material disposed below the trench between the second dielectric material lining the bottom of the trench and the bottom of the IMD layer, wherein the third dielectric material has the highest k value as compared with the first and second k values, and the width of the third dielectric material is 1/7 the width of the trench.

12. The method of claim 11 wherein the first dielectric material comprises an ultra low k (ULK) material and the second dielectric material comprises a low k (LK) material.

13. The method of claim 12 wherein the width of the LK material is 2/7 the width of the trench and the width of the ULK material is 5/7 the width of the trench.

14. The method of claim 11 wherein the IMD layer comprises a fourth material having a different k value than the first, second and third dielectric materials, the fourth material being disposed adjacent to the third dielectric material below the trench or the second dielectric material lining exposed sides of the via for reducing capacitance between parallel copper lines to reduce RC delay and improve circuit performance.

15. A method of forming a device comprising:
providing a substrate prepared with a dielectric layer; and
processing the dielectric layer to serve as an intermetal dielectric (IMD) layer, the IMD layer comprises at least a trench in a trench level and at least a via in a via level, wherein processing the dielectric layer comprises
providing a second dielectric material having a second k value, wherein the second dielectric material lines sidewalls and a bottom of the trench in the trench level and sidewalls of the via in the via level and also lines a bottom of the IMD layer,
providing a third dielectric material below the trench, wherein the third dielectric material is provided in between portions of the second dielectric material which line the bottom of the trench and the bottom of the IMD layer,
forming interconnects in the second dielectric material,
providing a first dielectric material between the interconnects

after forming the interconnects, wherein the first dielectric material comprises a first k value which is lower than the second k value, the second dielectric material surrounds and contacts sides and bottom surface of the first dielectric material, and the third dielectric material has the highest k value as compared with the first and second k values, and
processing the first and second dielectric materials such that top surfaces of the first dielectric material, the second dielectric material and the interconnects are coplanar with each other.

16. The method of claim 15 wherein processing the first and second dielectric materials comprises:
depositing a passivation layer covering the second dielectric material and surface of the interconnects after forming the interconnects; and
patterning the passivation layer to selectively cover the interconnects.

17. The method of c

Assignees

• Du Luying
• Zhang Fan
• Chen Jun
• Zhang Bei Chao
• Tan Juan Boon
• Globalfoundries Sg Pte Ltd

Inventors

• Du Luying
• Zhang Fan
• Chen Jun
• Zhang Bei Chao
• Tan Juan Boon

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/084

  for dual-damascene structures · CPC title