Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC

Patent metadata

Field	Value
Publication number	US-9489314-B2
Application number	US-201314061965-A
Country	US
Kind code	B2
Filing date	Oct 24, 2013
Priority date	Oct 24, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.

First claim

What is claimed is:

1. A data processing system comprising:
a plurality of processing cores, at least one processing core including cache memory for temporarily storing data;
a plurality of memory endpoints storing data;
a plurality of access arbitrators, one corresponding to each of said plurality of memory endpoints, each access arbitrator granting access to said corresponding memory endpoint to only single requesting processing core based upon a priority level, a fair share count and a starvation count corresponding to each processing core; and
a plurality of coherence units, one corresponding to each of said plurality of memory endpoints, each coherence unit including
a coherence maintenance address queue having a plurality of entries, each entry storing an address of an access request committed to the shared memory and an assigned ID tag,
an ID allocation block coupled to said coherence maintenance address queue assigning an available ID tag from a set of ID tags to an access committed to the shared memory for storage in said coherence maintenance address queue and retiring a coherence maintenance address queue entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding access, and
a comparator coupled to said input ports and said coherence maintenance address queue and receiving an address of a memory access request, said comparator comparing the address of the memory access request with all addresses stored in said coherence maintenance address queue and generating a hazard stall signal if the address of the memory access request matches any address stored in said coherence maintenance address queue.

2. The data processing system of claim 1 , wherein:
each of said access arbitrators includes a fair share count register corresponding to each processing core;
each of said access arbitrators grants access
to a single processing core requestor if only a single processing core requests access,
to a processing core presenting the highest priority level if plural processing cores request access simultaneously, and
to a processing core having the highest fair share count if plural processing cores having the same highest priority level request access simultaneously, incrementing said fair share count for any processing core having the same highest priority level not granted access and decrementing the processing core granted access by a number equal to a number of processing core having the same highest priority level not granted access.

3. The data processing system of claim 1 , wherein:
each of said access arbitrators includes a starvation count register and a writable starvation count reset register corresponding to each processing core;
each of said access arbitrators
decrements a starvation count register when a corresponding processing core requests access and is not granted access,
sets the priority level of a processing core to a highest level when said corresponding starvation count register reaches zero, and
resets a starvation count register to a value stored in a corresponding starvation count reset register upon grant of access to a corresponding processing core.

4. The data processing system of claim 1 , further comprising:
a data memory having a corresponding parity memory, sections of said parity memory storing an error detection and correction code for a corresponding section of said data memory;
an error detection and correction scrubber connected to said data memory and said parity memory, said error detection and correction scrubber operable to periodically calculate an error detection and correction code for a section of said data memory and compare the calculated parity value with an error detection and correction code stored in a corresponding section of said parity memory; and
a writable scrubbing period register storing a value controlling said periodicity of said error detection and correction scrubber.

5. The data processing system of claim 1 , wherein:
each of said coherence units further includes
a coherence transaction tracking queue having a plurality of entries, each entry storing dirty tags corresponding to coherence write data and an assigned ID tag,
a comparator connected to said coherence transaction tacking queue and receiving dirty tags corresponding to snoop response data, said comparator determining where snoop response dirty tags indicate dirty and said stored dirty tags indicate clean and inactive elsewhere, said comparator causing a write of received snoop response data that is dirty in the snoop response and clean in the coherence write data to the shared memory, and
said ID allocation block is further coupled to said coherence transaction tracking queue and operable to assign an available ID tag from said set of ID tags upon creation of an entry within said coherence transaction tracking queue.

6. The data processing system of claim 1 , wherein:
said ID allocation block assigns a lowest available ID tag upon allocating an ID tag.

7. A data processing system comprising:
a plurality of processing cores, at least one processing core including cache memory for temporarily storing data;
a plurality of memory endpoints storing data;
a plurality of access arbitrators, one corresponding to each of said plurality of memory endpoints, each access arbitrator granting access to said corresponding memory endpoint to only single requesting processing core based upon a priority level, a fair share count and a starvation count corresponding to each processing core; and
a memory translation unit including
a plurality of segment registers, each segment register including a first address field, a privilege identity field and a second address field,
a plurality of comparators receiving an address and a privilege identity tag from a processing core requesting access,
a multiplexer connected to said segment registers for selecting said second address field of a segment register having a first plurality of most significant bits matching said first address field and a privilege identity matching said privilege identity field;

wherein said memory translation unit forms a translated address having a first set of least significant bits corresponding to said address of said processing core requesting access and a second set of most significant bits corresponding to said second address field selected by said multiplexer.

Assignees

• Texas Instruments Inc

Inventors

• Chirca Kai
• Pierson Matthew D
• Anderson Timothy D

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• H04L63/0263

  Rule management · CPC title

• G06F13/1663

  Access to shared memory · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title