Printing minimum width features at non-minimum pitch and resulting device
US-2015130026-A1 · May 14, 2015 · US
Device resulting from printing minimum width semiconductor features at non-minimum pitch
US9484300B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9484300-B2 |
| Application number | US-201514953864-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 30, 2015 |
| Priority date | Nov 8, 2013 |
| Publication date | Nov 1, 2016 |
| Grant date | Nov 1, 2016 |
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Abstract
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Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: a semiconductor layer comprising a dummy shape, a first shape and a second shape, wherein the first shape has a minimum width within the semiconductor layer that is greater than a minimum pitch from the second shape having the minimum width, the dummy shape is provided in an intervening shape between the first shape and the second shape, and the dummy shape is at the minimum pitch from the first shape and the second shape and is at least the minimum width. 2. The apparatus according to claim 1 , wherein the dummy shape comprises a first portion and a second portion, the first portion being at the minimum pitch from the first shape and the second portion being at the minimum pitch from the second shape. 3. The apparatus according to claim 1 , wherein the semiconductor layer is a metal1 (M1) layer. 4. The apparatus according to claim 1 , wherein the semiconductor layer is formed by patterning a first hardmask according to the first shape, the second shape and the dummy shape during a first lithography-etch step. 5. The apparatus according to claim 4 , wherein the semiconductor layer is formed by patterning a second hardmask according to the intervening shape during a second lithography-etch step. 6. The apparatus according to claim 1 , the minimum width is 32 nm. 7. The apparatus according to claim 1 , the minimum pitch is 128 nm.
Assignees
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Classifications
- G06F30/39Primary
Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title
Elements for improving aerodynamics · CPC title
Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title
using masks for conductive or resistive materials · CPC title
Vias, e.g. via plugs · CPC title
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- What does patent US9484300B2 cover?
- Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a m…
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F30/39. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).