Face-up substrate integration with solder ball connection in semiconductor package

Patent metadata

Field	Value
Publication number	US-9468098-B2
Application number	US-201414220913-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Mar 20, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

First claim

What is claimed is:

1. A semiconductor package comprising:
a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate;
a laminate substrate with a second set of one or more package pads formed on a face of the laminate substrate; and
solder balls configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the 2D POG structure is placed face-up on the face of the laminate substrate,
wherein the solder balls are in direct electrical and mechanical contact with at least one of the first set of one or more package pads and at least one of the second set of one or more package pads.

2. The semiconductor package of claim 1 further comprising a printed circuit board (PCB), wherein the PCB is coupled to a bottom side of the laminate substrate.

3. The semiconductor package of claim 2 , wherein the PCB is coupled to the bottom side of the laminate substrate through land grid array (LGA) package pads formed on the bottom side of the laminate substrate.

4. The semiconductor package of claim 3 , wherein the passive component is separated from a ground plane of the PCB by the laminate substrate and the glass substrate.

5. The semiconductor package of claim 3 , wherein the LGA package pads on the bottom side of the laminate substrate are coupled to the second set of one or more package pads formed on the face of the laminate substrate through vias.

6. The semiconductor package of claim 1 , wherein the passive component is an inductor.

Assignees

• Qualcomm Inc

Inventors

• Kim Daeik Daniel
• Kim Jonghae
• Zuo Chengjie
• Yun Changhan Hobie
• Velez Mario Francisco
• Mikulka Robert Paul

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title