Low complexity high-order syndrome calculator for block codes and method of calculating high-order syndrome

Patent metadata

Field	Value
Publication number	US-9467174-B2
Application number	US-201414500803-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Mar 14, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A high-order syndrome calculator includes a serial-to-parallel converter configured to convert serial bit sequences received from a transmitter to a parallel multi-stream, an exclusive OR (XOR) operator configured to perform an XOR operation on bit values of the multi-stream, a zero interpolator configured to insert zero values between the bits on which the XOR operation is performed, and a linear feedback shift register configured to calculate a high-order syndrome value based on a coefficient of a remainder obtained by dividing, by a primitive polynomial, a polynomial generated from the multi-stream in which the zero values are inserted.

First claim

What is claimed is:

1. A high-order syndrome calculator comprising:
a serial-to-parallel converter configured to convert serial bit sequences received from a transmitter to a parallel multi-stream;
an exclusive OR (XOR) operator configured to perform an XOR operation on bit values of the parallel multi-stream;
a zero interpolator configured to insert zero values between the bit values on which the XOR operation is performed; and
a linear feedback shift register configured to calculate a high-order syndrome value based on a coefficient of a remainder obtained by dividing, by a primitive polynomial, a polynomial generated from the parallel multi-stream in which the zero values are inserted.

2. The high-order syndrome calculator of claim 1 , wherein the serial-to-parallel converter is further configured to convert the received serial bit sequences to an L-bit multi-stream, L denoting a natural number satisfying L≧1, by delaying the received serial bit sequences by integer multiples of a predetermined number of bits satisfying the equation D =n/j, where D denotes the predetermined number of bits, n denotes a block size of a block code, j denotes a syndrome order to be calculated, and n/j denotes an integer.

3. The high-order syndrome calculator of claim 2 , wherein the serial-to-parallel converter comprises (L−1) delay elements, and is further configured to output a bit sequence as a first bit of the multi-stream without delaying the bit sequence, and output the bit sequence as an L th bit of the multi-stream after delaying the bit sequence by (L−1) ×D bits.

4. The high-order syndrome calculator of claim 2 , wherein the serial-to-parallel converter is further configured to output the received serial bit sequences to the zero interpolator without delaying the received serial bit sequences in response to a value of n/j not being an integer.

5. The high-order syndrome calculator of claim 4 , wherein the zero interpolator is further configured to periodically insert N (=j−1) zero values between the bit values of the parallel multi-stream on which the XOR operation is performed in response to the value of n/j not being an integer.

6. The high-order syndrome calculator of claim 1 , wherein the zero interpolator is further configured to periodically insert N (=L−1) zero values between the bit values of the parallel multi-stream on which the XOR operation is performed.

7. A high-order syndrome calculator comprising:
a serial-to-parallel converter configured to convert serial bit sequences received from a transmitter to a parallel multi-stream configured based on a symbol unit, wherein the symbol unit comprises a plurality of bits;
an exclusive OR (XOR) operator configured to perform an XOR operation on bit values of the parallel multi-stream based on the symbol unit;
a zero interpolator configured to insert zero values between the bit values of the parallel multi-stream on which the XOR operation is performed; and
a linear feedback shift register configured to calculate a high-order syndrome value based on a coefficient of a remainder obtained by dividing, by a primitive polynomial, a polynomial generated from the parallel multi-stream in which the zero values are inserted.

8. The high-order syndrome calculator of claim 7 , wherein the serial-to-parallel converter is further configured to convert the received serial bit sequences to a (symbol unit ×L)-bit multi-stream, L denoting a natural number satisfying L≧1, by delaying the received serial bit sequences by integer multiples of a predetermined number of bits satisfying the equation D =n/j, where D denotes the predetermined number of bits, n denotes a block size of a block code, j denotes a syndrome order to be calculated, and n/j denotes an integer.

9. The high-order syndrome calculator of claim 8 , wherein the serial-to-parallel converter is further configured to output the received serial bit sequences to the zero interpolator without delaying the received serial bit sequences in response to a value of n/j not being an integer.

10. The high-order syndrome calculator of claim 9 , wherein the zero interpolator is further configured to periodically insert N (=j−1) zero values of the symbol unit between the bit values of the parallel multi-stream on which the XOR operation is performed in response to the value of n/j not being an integer.

11. The high-order syndrome calculator of claim 7 , wherein the zero interpolator is further configured to periodically insert N (=L−1) zero values of the symbol unit between the bit values of the parallel multi-stream on which the XOR operation is performed.

12. A method of calculating a high-order syndrome, the method comprising:
converting serial bit sequences received from a transmitter to a parallel multi-stream;
performing an exclusive OR (XOR) operation on bit values of the parallel multi-stream;
inserting zero values between the bit values on which the XOR operation is performed; and
calculating a high-order syndrome value based on a coefficient of a remainder obtained by dividing, by a primitive polynomial, a polynomial generated from the parallel multi-stream in which the zero values are inserted.

13. A non-transitory computer-readable storage medium storing a program comprising instructions to control a computer to perform the method of claim 12 .

14. A method of calculating a high-order syndrome, the method comprising:
converting serial bit sequences received from a transmitter to a parallel multi-stream configured based on a symbol unit, wherein the symbol unit comprises a plurality of bits;
performing an exclusive OR (XOR) operation on bit values of the parallel multi-stream based on the symbol unit;
inserting zero values between the bit values of the parallel multi-stream on which the XOR operation is performed; and
calculating a high-order syndrome value based on a coefficient of a remainder obtained by dividing, by a primitive polynomial, a polynomial generated from the parallel multi-stream in which the zero values are inserted.

15. A non-transitory computer-readable storage medium storing a program comprising instructions to control a computer to perform the method of claim 14 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Chang Soon
• Hwang Hyo Sun
• Hong Young Jun

Classifications

• H04L7/0029

  interpolation of received data signal · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title

• H03M13/1545

  Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial · CPC title

• H03M13/1595

  Parallel or block-wise remainder calculation · CPC title

• H04L25/03872

  Parallel scrambling or descrambling · CPC title